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jfs: Simplify code
[linux/fpc-iii.git] / drivers / edac / altera_edac.c
blob2398d0701f5b0dad1f5eb98a32f093a668c95844
1 /*
2 * Copyright Altera Corporation (C) 2014-2016. All rights reserved.
3 * Copyright 2011-2012 Calxeda, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 *
17 * Adapted from the highbank_mc_edac driver.
18 */
19
20 #include <asm/cacheflush.h>
21 #include <linux/ctype.h>
22 #include <linux/delay.h>
23 #include <linux/edac.h>
24 #include <linux/genalloc.h>
25 #include <linux/interrupt.h>
26 #include <linux/irqchip/chained_irq.h>
27 #include <linux/kernel.h>
28 #include <linux/mfd/syscon.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_platform.h>
32 #include <linux/platform_device.h>
33 #include <linux/regmap.h>
34 #include <linux/types.h>
35 #include <linux/uaccess.h>
36
37 #include "altera_edac.h"
38 #include "edac_core.h"
39 #include "edac_module.h"
40
41 #define EDAC_MOD_STR "altera_edac"
42 #define EDAC_VERSION "1"
43 #define EDAC_DEVICE "Altera"
44
45 static const struct altr_sdram_prv_data c5_data = {
46 .ecc_ctrl_offset = CV_CTLCFG_OFST,
47 .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN,
48 .ecc_stat_offset = CV_DRAMSTS_OFST,
49 .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR,
50 .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR,
51 .ecc_saddr_offset = CV_ERRADDR_OFST,
52 .ecc_daddr_offset = CV_ERRADDR_OFST,
53 .ecc_cecnt_offset = CV_SBECOUNT_OFST,
54 .ecc_uecnt_offset = CV_DBECOUNT_OFST,
55 .ecc_irq_en_offset = CV_DRAMINTR_OFST,
56 .ecc_irq_en_mask = CV_DRAMINTR_INTREN,
57 .ecc_irq_clr_offset = CV_DRAMINTR_OFST,
58 .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN),
59 .ecc_cnt_rst_offset = CV_DRAMINTR_OFST,
60 .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR,
61 .ce_ue_trgr_offset = CV_CTLCFG_OFST,
62 .ce_set_mask = CV_CTLCFG_GEN_SB_ERR,
63 .ue_set_mask = CV_CTLCFG_GEN_DB_ERR,
64 };
65
66 static const struct altr_sdram_prv_data a10_data = {
67 .ecc_ctrl_offset = A10_ECCCTRL1_OFST,
68 .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN,
69 .ecc_stat_offset = A10_INTSTAT_OFST,
70 .ecc_stat_ce_mask = A10_INTSTAT_SBEERR,
71 .ecc_stat_ue_mask = A10_INTSTAT_DBEERR,
72 .ecc_saddr_offset = A10_SERRADDR_OFST,
73 .ecc_daddr_offset = A10_DERRADDR_OFST,
74 .ecc_irq_en_offset = A10_ERRINTEN_OFST,
75 .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK,
76 .ecc_irq_clr_offset = A10_INTSTAT_OFST,
77 .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
78 .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST,
79 .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK,
80 .ce_ue_trgr_offset = A10_DIAGINTTEST_OFST,
81 .ce_set_mask = A10_DIAGINT_TSERRA_MASK,
82 .ue_set_mask = A10_DIAGINT_TDERRA_MASK,
83 };
84
85 /*********************** EDAC Memory Controller Functions ****************/
86
87 /* The SDRAM controller uses the EDAC Memory Controller framework. */
88
89 static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
90 {
91 struct mem_ctl_info *mci = dev_id;
92 struct altr_sdram_mc_data *drvdata = mci->pvt_info;
93 const struct altr_sdram_prv_data *priv = drvdata->data;
94 u32 status, err_count = 1, err_addr;
95
96 regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status);
97
98 if (status & priv->ecc_stat_ue_mask) {
99 regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset,
100 &err_addr);
101 if (priv->ecc_uecnt_offset)
102 regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,
103 &err_count);
104 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
105 err_count, err_addr);
106 }
107 if (status & priv->ecc_stat_ce_mask) {
108 regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset,
109 &err_addr);
110 if (priv->ecc_uecnt_offset)
111 regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset,
112 &err_count);
113 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
114 err_addr >> PAGE_SHIFT,
115 err_addr & ~PAGE_MASK, 0,
116 0, 0, -1, mci->ctl_name, "");
117 /* Clear IRQ to resume */
118 regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset,
119 priv->ecc_irq_clr_mask);
120
121 return IRQ_HANDLED;
122 }
123 return IRQ_NONE;
124 }
125
126 static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
127 const char __user *data,
128 size_t count, loff_t *ppos)
129 {
130 struct mem_ctl_info *mci = file->private_data;
131 struct altr_sdram_mc_data *drvdata = mci->pvt_info;
132 const struct altr_sdram_prv_data *priv = drvdata->data;
133 u32 *ptemp;
134 dma_addr_t dma_handle;
135 u32 reg, read_reg;
136
137 ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);
138 if (!ptemp) {
139 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
140 edac_printk(KERN_ERR, EDAC_MC,
141 "Inject: Buffer Allocation error\n");
142 return -ENOMEM;
143 }
144
145 regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
146 &read_reg);
147 read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask);
148
149 /* Error are injected by writing a word while the SBE or DBE
150 * bit in the CTLCFG register is set. Reading the word will
151 * trigger the SBE or DBE error and the corresponding IRQ.
152 */
153 if (count == 3) {
154 edac_printk(KERN_ALERT, EDAC_MC,
155 "Inject Double bit error\n");
156 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
157 (read_reg | priv->ue_set_mask));
158 } else {
159 edac_printk(KERN_ALERT, EDAC_MC,
160 "Inject Single bit error\n");
161 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
162 (read_reg | priv->ce_set_mask));
163 }
164
165 ptemp[0] = 0x5A5A5A5A;
166 ptemp[1] = 0xA5A5A5A5;
167
168 /* Clear the error injection bits */
169 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg);
170 /* Ensure it has been written out */
171 wmb();
172
173 /*
174 * To trigger the error, we need to read the data back
175 * (the data was written with errors above).
176 * The ACCESS_ONCE macros and printk are used to prevent the
177 * the compiler optimizing these reads out.
178 */
179 reg = ACCESS_ONCE(ptemp[0]);
180 read_reg = ACCESS_ONCE(ptemp[1]);
181 /* Force Read */
182 rmb();
183
184 edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",
185 reg, read_reg);
186
187 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
188
189 return count;
190 }
191
192 static const struct file_operations altr_sdr_mc_debug_inject_fops = {
193 .open = simple_open,
194 .write = altr_sdr_mc_err_inject_write,
195 .llseek = generic_file_llseek,
196 };
197
198 static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
199 {
200 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
201 return;
202
203 if (!mci->debugfs)
204 return;
205
206 edac_debugfs_create_file("inject_ctrl", S_IWUSR, mci->debugfs, mci,
207 &altr_sdr_mc_debug_inject_fops);
208 }
209
210 /* Get total memory size from Open Firmware DTB */
211 static unsigned long get_total_mem(void)
212 {
213 struct device_node *np = NULL;
214 const unsigned int *reg, *reg_end;
215 int len, sw, aw;
216 unsigned long start, size, total_mem = 0;
217
218 for_each_node_by_type(np, "memory") {
219 aw = of_n_addr_cells(np);
220 sw = of_n_size_cells(np);
221 reg = (const unsigned int *)of_get_property(np, "reg", &len);
222 reg_end = reg + (len / sizeof(u32));
223
224 total_mem = 0;
225 do {
226 start = of_read_number(reg, aw);
227 reg += aw;
228 size = of_read_number(reg, sw);
229 reg += sw;
230 total_mem += size;
231 } while (reg < reg_end);
232 }
233 edac_dbg(0, "total_mem 0x%lx\n", total_mem);
234 return total_mem;
235 }
236
237 static const struct of_device_id altr_sdram_ctrl_of_match[] = {
238 { .compatible = "altr,sdram-edac", .data = &c5_data},
239 { .compatible = "altr,sdram-edac-a10", .data = &a10_data},
240 {},
241 };
242 MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
243
244 static int a10_init(struct regmap *mc_vbase)
245 {
246 if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST,
247 A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) {
248 edac_printk(KERN_ERR, EDAC_MC,
249 "Error setting SB IRQ mode\n");
250 return -ENODEV;
251 }
252
253 if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) {
254 edac_printk(KERN_ERR, EDAC_MC,
255 "Error setting trigger count\n");
256 return -ENODEV;
257 }
258
259 return 0;
260 }
261
262 static int a10_unmask_irq(struct platform_device *pdev, u32 mask)
263 {
264 void __iomem *sm_base;
265 int ret = 0;
266
267 if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32),
268 dev_name(&pdev->dev))) {
269 edac_printk(KERN_ERR, EDAC_MC,
270 "Unable to request mem region\n");
271 return -EBUSY;
272 }
273
274 sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32));
275 if (!sm_base) {
276 edac_printk(KERN_ERR, EDAC_MC,
277 "Unable to ioremap device\n");
278
279 ret = -ENOMEM;
280 goto release;
281 }
282
283 iowrite32(mask, sm_base);
284
285 iounmap(sm_base);
286
287 release:
288 release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32));
289
290 return ret;
291 }
292
293 static int altr_sdram_probe(struct platform_device *pdev)
294 {
295 const struct of_device_id *id;
296 struct edac_mc_layer layers[2];
297 struct mem_ctl_info *mci;
298 struct altr_sdram_mc_data *drvdata;
299 const struct altr_sdram_prv_data *priv;
300 struct regmap *mc_vbase;
301 struct dimm_info *dimm;
302 u32 read_reg;
303 int irq, irq2, res = 0;
304 unsigned long mem_size, irqflags = 0;
305
306 id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
307 if (!id)
308 return -ENODEV;
309
310 /* Grab the register range from the sdr controller in device tree */
311 mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
312 "altr,sdr-syscon");
313 if (IS_ERR(mc_vbase)) {
314 edac_printk(KERN_ERR, EDAC_MC,
315 "regmap for altr,sdr-syscon lookup failed.\n");
316 return -ENODEV;
317 }
318
319 /* Check specific dependencies for the module */
320 priv = of_match_node(altr_sdram_ctrl_of_match,
321 pdev->dev.of_node)->data;
322
323 /* Validate the SDRAM controller has ECC enabled */
324 if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) ||
325 ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
326 edac_printk(KERN_ERR, EDAC_MC,
327 "No ECC/ECC disabled [0x%08X]\n", read_reg);
328 return -ENODEV;
329 }
330
331 /* Grab memory size from device tree. */
332 mem_size = get_total_mem();
333 if (!mem_size) {
334 edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
335 return -ENODEV;
336 }
337
338 /* Ensure the SDRAM Interrupt is disabled */
339 if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset,
340 priv->ecc_irq_en_mask, 0)) {
341 edac_printk(KERN_ERR, EDAC_MC,
342 "Error disabling SDRAM ECC IRQ\n");
343 return -ENODEV;
344 }
345
346 /* Toggle to clear the SDRAM Error count */
347 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
348 priv->ecc_cnt_rst_mask,
349 priv->ecc_cnt_rst_mask)) {
350 edac_printk(KERN_ERR, EDAC_MC,
351 "Error clearing SDRAM ECC count\n");
352 return -ENODEV;
353 }
354
355 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
356 priv->ecc_cnt_rst_mask, 0)) {
357 edac_printk(KERN_ERR, EDAC_MC,
358 "Error clearing SDRAM ECC count\n");
359 return -ENODEV;
360 }
361
362 irq = platform_get_irq(pdev, 0);
363 if (irq < 0) {
364 edac_printk(KERN_ERR, EDAC_MC,
365 "No irq %d in DT\n", irq);
366 return -ENODEV;
367 }
368
369 /* Arria10 has a 2nd IRQ */
370 irq2 = platform_get_irq(pdev, 1);
371
372 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
373 layers[0].size = 1;
374 layers[0].is_virt_csrow = true;
375 layers[1].type = EDAC_MC_LAYER_CHANNEL;
376 layers[1].size = 1;
377 layers[1].is_virt_csrow = false;
378 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
379 sizeof(struct altr_sdram_mc_data));
380 if (!mci)
381 return -ENOMEM;
382
383 mci->pdev = &pdev->dev;
384 drvdata = mci->pvt_info;
385 drvdata->mc_vbase = mc_vbase;
386 drvdata->data = priv;
387 platform_set_drvdata(pdev, mci);
388
389 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
390 edac_printk(KERN_ERR, EDAC_MC,
391 "Unable to get managed device resource\n");
392 res = -ENOMEM;
393 goto free;
394 }
395
396 mci->mtype_cap = MEM_FLAG_DDR3;
397 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
398 mci->edac_cap = EDAC_FLAG_SECDED;
399 mci->mod_name = EDAC_MOD_STR;
400 mci->mod_ver = EDAC_VERSION;
401 mci->ctl_name = dev_name(&pdev->dev);
402 mci->scrub_mode = SCRUB_SW_SRC;
403 mci->dev_name = dev_name(&pdev->dev);
404
405 dimm = *mci->dimms;
406 dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
407 dimm->grain = 8;
408 dimm->dtype = DEV_X8;
409 dimm->mtype = MEM_DDR3;
410 dimm->edac_mode = EDAC_SECDED;
411
412 res = edac_mc_add_mc(mci);
413 if (res < 0)
414 goto err;
415
416 /* Only the Arria10 has separate IRQs */
417 if (irq2 > 0) {
418 /* Arria10 specific initialization */
419 res = a10_init(mc_vbase);
420 if (res < 0)
421 goto err2;
422
423 res = devm_request_irq(&pdev->dev, irq2,
424 altr_sdram_mc_err_handler,
425 IRQF_SHARED, dev_name(&pdev->dev), mci);
426 if (res < 0) {
427 edac_mc_printk(mci, KERN_ERR,
428 "Unable to request irq %d\n", irq2);
429 res = -ENODEV;
430 goto err2;
431 }
432
433 res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK);
434 if (res < 0)
435 goto err2;
436
437 irqflags = IRQF_SHARED;
438 }
439
440 res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
441 irqflags, dev_name(&pdev->dev), mci);
442 if (res < 0) {
443 edac_mc_printk(mci, KERN_ERR,
444 "Unable to request irq %d\n", irq);
445 res = -ENODEV;
446 goto err2;
447 }
448
449 /* Infrastructure ready - enable the IRQ */
450 if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
451 priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
452 edac_mc_printk(mci, KERN_ERR,
453 "Error enabling SDRAM ECC IRQ\n");
454 res = -ENODEV;
455 goto err2;
456 }
457
458 altr_sdr_mc_create_debugfs_nodes(mci);
459
460 devres_close_group(&pdev->dev, NULL);
461
462 return 0;
463
464 err2:
465 edac_mc_del_mc(&pdev->dev);
466 err:
467 devres_release_group(&pdev->dev, NULL);
468 free:
469 edac_mc_free(mci);
470 edac_printk(KERN_ERR, EDAC_MC,
471 "EDAC Probe Failed; Error %d\n", res);
472
473 return res;
474 }
475
476 static int altr_sdram_remove(struct platform_device *pdev)
477 {
478 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
479
480 edac_mc_del_mc(&pdev->dev);
481 edac_mc_free(mci);
482 platform_set_drvdata(pdev, NULL);
483
484 return 0;
485 }
486
487 /*
488 * If you want to suspend, need to disable EDAC by removing it
489 * from the device tree or defconfig.
490 */
491 #ifdef CONFIG_PM
492 static int altr_sdram_prepare(struct device *dev)
493 {
494 pr_err("Suspend not allowed when EDAC is enabled.\n");
495
496 return -EPERM;
497 }
498
499 static const struct dev_pm_ops altr_sdram_pm_ops = {
500 .prepare = altr_sdram_prepare,
501 };
502 #endif
503
504 static struct platform_driver altr_sdram_edac_driver = {
505 .probe = altr_sdram_probe,
506 .remove = altr_sdram_remove,
507 .driver = {
508 .name = "altr_sdram_edac",
509 #ifdef CONFIG_PM
510 .pm = &altr_sdram_pm_ops,
511 #endif
512 .of_match_table = altr_sdram_ctrl_of_match,
513 },
514 };
515
516 module_platform_driver(altr_sdram_edac_driver);
517
518 /************************* EDAC Parent Probe *************************/
519
520 static const struct of_device_id altr_edac_device_of_match[];
521
522 static const struct of_device_id altr_edac_of_match[] = {
523 { .compatible = "altr,socfpga-ecc-manager" },
524 {},
525 };
526 MODULE_DEVICE_TABLE(of, altr_edac_of_match);
527
528 static int altr_edac_probe(struct platform_device *pdev)
529 {
530 of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match,
531 NULL, &pdev->dev);
532 return 0;
533 }
534
535 static struct platform_driver altr_edac_driver = {
536 .probe = altr_edac_probe,
537 .driver = {
538 .name = "socfpga_ecc_manager",
539 .of_match_table = altr_edac_of_match,
540 },
541 };
542 module_platform_driver(altr_edac_driver);
543
544 /************************* EDAC Device Functions *************************/
545
546 /*
547 * EDAC Device Functions (shared between various IPs).
548 * The discrete memories use the EDAC Device framework. The probe
549 * and error handling functions are very similar between memories
550 * so they are shared. The memory allocation and freeing for EDAC
551 * trigger testing are different for each memory.
552 */
553
554 static const struct edac_device_prv_data ocramecc_data;
555 static const struct edac_device_prv_data l2ecc_data;
556 static const struct edac_device_prv_data a10_ocramecc_data;
557 static const struct edac_device_prv_data a10_l2ecc_data;
558
559 static irqreturn_t altr_edac_device_handler(int irq, void *dev_id)
560 {
561 irqreturn_t ret_value = IRQ_NONE;
562 struct edac_device_ctl_info *dci = dev_id;
563 struct altr_edac_device_dev *drvdata = dci->pvt_info;
564 const struct edac_device_prv_data *priv = drvdata->data;
565
566 if (irq == drvdata->sb_irq) {
567 if (priv->ce_clear_mask)
568 writel(priv->ce_clear_mask, drvdata->base);
569 edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name);
570 ret_value = IRQ_HANDLED;
571 } else if (irq == drvdata->db_irq) {
572 if (priv->ue_clear_mask)
573 writel(priv->ue_clear_mask, drvdata->base);
574 edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name);
575 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
576 ret_value = IRQ_HANDLED;
577 } else {
578 WARN_ON(1);
579 }
580
581 return ret_value;
582 }
583
584 static ssize_t altr_edac_device_trig(struct file *file,
585 const char __user *user_buf,
586 size_t count, loff_t *ppos)
587
588 {
589 u32 *ptemp, i, error_mask;
590 int result = 0;
591 u8 trig_type;
592 unsigned long flags;
593 struct edac_device_ctl_info *edac_dci = file->private_data;
594 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
595 const struct edac_device_prv_data *priv = drvdata->data;
596 void *generic_ptr = edac_dci->dev;
597
598 if (!user_buf || get_user(trig_type, user_buf))
599 return -EFAULT;
600
601 if (!priv->alloc_mem)
602 return -ENOMEM;
603
604 /*
605 * Note that generic_ptr is initialized to the device * but in
606 * some alloc_functions, this is overridden and returns data.
607 */
608 ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr);
609 if (!ptemp) {
610 edac_printk(KERN_ERR, EDAC_DEVICE,
611 "Inject: Buffer Allocation error\n");
612 return -ENOMEM;
613 }
614
615 if (trig_type == ALTR_UE_TRIGGER_CHAR)
616 error_mask = priv->ue_set_mask;
617 else
618 error_mask = priv->ce_set_mask;
619
620 edac_printk(KERN_ALERT, EDAC_DEVICE,
621 "Trigger Error Mask (0x%X)\n", error_mask);
622
623 local_irq_save(flags);
624 /* write ECC corrupted data out. */
625 for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) {
626 /* Read data so we're in the correct state */
627 rmb();
628 if (ACCESS_ONCE(ptemp[i]))
629 result = -1;
630 /* Toggle Error bit (it is latched), leave ECC enabled */
631 writel(error_mask, (drvdata->base + priv->set_err_ofst));
632 writel(priv->ecc_enable_mask, (drvdata->base +
633 priv->set_err_ofst));
634 ptemp[i] = i;
635 }
636 /* Ensure it has been written out */
637 wmb();
638 local_irq_restore(flags);
639
640 if (result)
641 edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n");
642
643 /* Read out written data. ECC error caused here */
644 for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++)
645 if (ACCESS_ONCE(ptemp[i]) != i)
646 edac_printk(KERN_ERR, EDAC_DEVICE,
647 "Read doesn't match written data\n");
648
649 if (priv->free_mem)
650 priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr);
651
652 return count;
653 }
654
655 static const struct file_operations altr_edac_device_inject_fops = {
656 .open = simple_open,
657 .write = altr_edac_device_trig,
658 .llseek = generic_file_llseek,
659 };
660
661 static ssize_t altr_edac_a10_device_trig(struct file *file,
662 const char __user *user_buf,
663 size_t count, loff_t *ppos);
664
665 static const struct file_operations altr_edac_a10_device_inject_fops = {
666 .open = simple_open,
667 .write = altr_edac_a10_device_trig,
668 .llseek = generic_file_llseek,
669 };
670
671 static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci,
672 const struct edac_device_prv_data *priv)
673 {
674 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
675
676 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
677 return;
678
679 drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name);
680 if (!drvdata->debugfs_dir)
681 return;
682
683 if (!edac_debugfs_create_file(priv->dbgfs_name, S_IWUSR,
684 drvdata->debugfs_dir, edac_dci,
685 priv->inject_fops))
686 debugfs_remove_recursive(drvdata->debugfs_dir);
687 }
688
689 static const struct of_device_id altr_edac_device_of_match[] = {
690 #ifdef CONFIG_EDAC_ALTERA_L2C
691 { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data },
692 #endif
693 #ifdef CONFIG_EDAC_ALTERA_OCRAM
694 { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data },
695 #endif
696 {},
697 };
698 MODULE_DEVICE_TABLE(of, altr_edac_device_of_match);
699
700 /*
701 * altr_edac_device_probe()
702 * This is a generic EDAC device driver that will support
703 * various Altera memory devices such as the L2 cache ECC and
704 * OCRAM ECC as well as the memories for other peripherals.
705 * Module specific initialization is done by passing the
706 * function index in the device tree.
707 */
708 static int altr_edac_device_probe(struct platform_device *pdev)
709 {
710 struct edac_device_ctl_info *dci;
711 struct altr_edac_device_dev *drvdata;
712 struct resource *r;
713 int res = 0;
714 struct device_node *np = pdev->dev.of_node;
715 char *ecc_name = (char *)np->name;
716 static int dev_instance;
717
718 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
719 edac_printk(KERN_ERR, EDAC_DEVICE,
720 "Unable to open devm\n");
721 return -ENOMEM;
722 }
723
724 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
725 if (!r) {
726 edac_printk(KERN_ERR, EDAC_DEVICE,
727 "Unable to get mem resource\n");
728 res = -ENODEV;
729 goto fail;
730 }
731
732 if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
733 dev_name(&pdev->dev))) {
734 edac_printk(KERN_ERR, EDAC_DEVICE,
735 "%s:Error requesting mem region\n", ecc_name);
736 res = -EBUSY;
737 goto fail;
738 }
739
740 dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name,
741 1, ecc_name, 1, 0, NULL, 0,
742 dev_instance++);
743
744 if (!dci) {
745 edac_printk(KERN_ERR, EDAC_DEVICE,
746 "%s: Unable to allocate EDAC device\n", ecc_name);
747 res = -ENOMEM;
748 goto fail;
749 }
750
751 drvdata = dci->pvt_info;
752 dci->dev = &pdev->dev;
753 platform_set_drvdata(pdev, dci);
754 drvdata->edac_dev_name = ecc_name;
755
756 drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
757 if (!drvdata->base)
758 goto fail1;
759
760 /* Get driver specific data for this EDAC device */
761 drvdata->data = of_match_node(altr_edac_device_of_match, np)->data;
762
763 /* Check specific dependencies for the module */
764 if (drvdata->data->setup) {
765 res = drvdata->data->setup(drvdata);
766 if (res)
767 goto fail1;
768 }
769
770 drvdata->sb_irq = platform_get_irq(pdev, 0);
771 res = devm_request_irq(&pdev->dev, drvdata->sb_irq,
772 altr_edac_device_handler,
773 0, dev_name(&pdev->dev), dci);
774 if (res)
775 goto fail1;
776
777 drvdata->db_irq = platform_get_irq(pdev, 1);
778 res = devm_request_irq(&pdev->dev, drvdata->db_irq,
779 altr_edac_device_handler,
780 0, dev_name(&pdev->dev), dci);
781 if (res)
782 goto fail1;
783
784 dci->mod_name = "Altera ECC Manager";
785 dci->dev_name = drvdata->edac_dev_name;
786
787 res = edac_device_add_device(dci);
788 if (res)
789 goto fail1;
790
791 altr_create_edacdev_dbgfs(dci, drvdata->data);
792
793 devres_close_group(&pdev->dev, NULL);
794
795 return 0;
796
797 fail1:
798 edac_device_free_ctl_info(dci);
799 fail:
800 devres_release_group(&pdev->dev, NULL);
801 edac_printk(KERN_ERR, EDAC_DEVICE,
802 "%s:Error setting up EDAC device: %d\n", ecc_name, res);
803
804 return res;
805 }
806
807 static int altr_edac_device_remove(struct platform_device *pdev)
808 {
809 struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);
810 struct altr_edac_device_dev *drvdata = dci->pvt_info;
811
812 debugfs_remove_recursive(drvdata->debugfs_dir);
813 edac_device_del_device(&pdev->dev);
814 edac_device_free_ctl_info(dci);
815
816 return 0;
817 }
818
819 static struct platform_driver altr_edac_device_driver = {
820 .probe = altr_edac_device_probe,
821 .remove = altr_edac_device_remove,
822 .driver = {
823 .name = "altr_edac_device",
824 .of_match_table = altr_edac_device_of_match,
825 },
826 };
827 module_platform_driver(altr_edac_device_driver);
828
829 /******************* Arria10 Device ECC Shared Functions *****************/
830
831 /*
832 * Test for memory's ECC dependencies upon entry because platform specific
833 * startup should have initialized the memory and enabled the ECC.
834 * Can't turn on ECC here because accessing un-initialized memory will
835 * cause CE/UE errors possibly causing an ABORT.
836 */
837 static int __maybe_unused
838 altr_check_ecc_deps(struct altr_edac_device_dev *device)
839 {
840 void __iomem *base = device->base;
841 const struct edac_device_prv_data *prv = device->data;
842
843 if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask)
844 return 0;
845
846 edac_printk(KERN_ERR, EDAC_DEVICE,
847 "%s: No ECC present or ECC disabled.\n",
848 device->edac_dev_name);
849 return -ENODEV;
850 }
851
852 static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id)
853 {
854 struct altr_edac_device_dev *dci = dev_id;
855 void __iomem *base = dci->base;
856
857 if (irq == dci->sb_irq) {
858 writel(ALTR_A10_ECC_SERRPENA,
859 base + ALTR_A10_ECC_INTSTAT_OFST);
860 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
861
862 return IRQ_HANDLED;
863 } else if (irq == dci->db_irq) {
864 writel(ALTR_A10_ECC_DERRPENA,
865 base + ALTR_A10_ECC_INTSTAT_OFST);
866 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
867 if (dci->data->panic)
868 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
869
870 return IRQ_HANDLED;
871 }
872
873 WARN_ON(1);
874
875 return IRQ_NONE;
876 }
877
878 /******************* Arria10 Memory Buffer Functions *********************/
879
880 static inline int a10_get_irq_mask(struct device_node *np)
881 {
882 int irq;
883 const u32 *handle = of_get_property(np, "interrupts", NULL);
884
885 if (!handle)
886 return -ENODEV;
887 irq = be32_to_cpup(handle);
888 return irq;
889 }
890
891 static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr)
892 {
893 u32 value = readl(ioaddr);
894
895 value |= bit_mask;
896 writel(value, ioaddr);
897 }
898
899 static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr)
900 {
901 u32 value = readl(ioaddr);
902
903 value &= ~bit_mask;
904 writel(value, ioaddr);
905 }
906
907 static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr)
908 {
909 u32 value = readl(ioaddr);
910
911 return (value & bit_mask) ? 1 : 0;
912 }
913
914 /*
915 * This function uses the memory initialization block in the Arria10 ECC
916 * controller to initialize/clear the entire memory data and ECC data.
917 */
918 static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port)
919 {
920 int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US;
921 u32 init_mask, stat_mask, clear_mask;
922 int ret = 0;
923
924 if (port) {
925 init_mask = ALTR_A10_ECC_INITB;
926 stat_mask = ALTR_A10_ECC_INITCOMPLETEB;
927 clear_mask = ALTR_A10_ECC_ERRPENB_MASK;
928 } else {
929 init_mask = ALTR_A10_ECC_INITA;
930 stat_mask = ALTR_A10_ECC_INITCOMPLETEA;
931 clear_mask = ALTR_A10_ECC_ERRPENA_MASK;
932 }
933
934 ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST));
935 while (limit--) {
936 if (ecc_test_bits(stat_mask,
937 (ioaddr + ALTR_A10_ECC_INITSTAT_OFST)))
938 break;
939 udelay(1);
940 }
941 if (limit < 0)
942 ret = -EBUSY;
943
944 /* Clear any pending ECC interrupts */
945 writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST));
946
947 return ret;
948 }
949
950 static __init int __maybe_unused
951 altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask,
952 u32 ecc_ctrl_en_mask, bool dual_port)
953 {
954 int ret = 0;
955 void __iomem *ecc_block_base;
956 struct regmap *ecc_mgr_map;
957 char *ecc_name;
958 struct device_node *np_eccmgr;
959
960 ecc_name = (char *)np->name;
961
962 /* Get the ECC Manager - parent of the device EDACs */
963 np_eccmgr = of_get_parent(np);
964 ecc_mgr_map = syscon_regmap_lookup_by_phandle(np_eccmgr,
965 "altr,sysmgr-syscon");
966 of_node_put(np_eccmgr);
967 if (IS_ERR(ecc_mgr_map)) {
968 edac_printk(KERN_ERR, EDAC_DEVICE,
969 "Unable to get syscon altr,sysmgr-syscon\n");
970 return -ENODEV;
971 }
972
973 /* Map the ECC Block */
974 ecc_block_base = of_iomap(np, 0);
975 if (!ecc_block_base) {
976 edac_printk(KERN_ERR, EDAC_DEVICE,
977 "Unable to map %s ECC block\n", ecc_name);
978 return -ENODEV;
979 }
980
981 /* Disable ECC */
982 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask);
983 writel(ALTR_A10_ECC_SERRINTEN,
984 (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST));
985 ecc_clear_bits(ecc_ctrl_en_mask,
986 (ecc_block_base + ALTR_A10_ECC_CTRL_OFST));
987 /* Ensure all writes complete */
988 wmb();
989 /* Use HW initialization block to initialize memory for ECC */
990 ret = altr_init_memory_port(ecc_block_base, 0);
991 if (ret) {
992 edac_printk(KERN_ERR, EDAC_DEVICE,
993 "ECC: cannot init %s PORTA memory\n", ecc_name);
994 goto out;
995 }
996
997 if (dual_port) {
998 ret = altr_init_memory_port(ecc_block_base, 1);
999 if (ret) {
1000 edac_printk(KERN_ERR, EDAC_DEVICE,
1001 "ECC: cannot init %s PORTB memory\n",
1002 ecc_name);
1003 goto out;
1004 }
1005 }
1006
1007 /* Interrupt mode set to every SBERR */
1008 regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST,
1009 ALTR_A10_ECC_INTMODE);
1010 /* Enable ECC */
1011 ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base +
1012 ALTR_A10_ECC_CTRL_OFST));
1013 writel(ALTR_A10_ECC_SERRINTEN,
1014 (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST));
1015 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask);
1016 /* Ensure all writes complete */
1017 wmb();
1018 out:
1019 iounmap(ecc_block_base);
1020 return ret;
1021 }
1022
1023 static int validate_parent_available(struct device_node *np);
1024 static const struct of_device_id altr_edac_a10_device_of_match[];
1025 static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat)
1026 {
1027 int irq;
1028 struct device_node *child, *np = of_find_compatible_node(NULL, NULL,
1029 "altr,socfpga-a10-ecc-manager");
1030 if (!np) {
1031 edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n");
1032 return -ENODEV;
1033 }
1034
1035 for_each_child_of_node(np, child) {
1036 const struct of_device_id *pdev_id;
1037 const struct edac_device_prv_data *prv;
1038
1039 if (!of_device_is_available(child))
1040 continue;
1041 if (!of_device_is_compatible(child, compat))
1042 continue;
1043
1044 if (validate_parent_available(child))
1045 continue;
1046
1047 irq = a10_get_irq_mask(child);
1048 if (irq < 0)
1049 continue;
1050
1051 /* Get matching node and check for valid result */
1052 pdev_id = of_match_node(altr_edac_a10_device_of_match, child);
1053 if (IS_ERR_OR_NULL(pdev_id))
1054 continue;
1055
1056 /* Validate private data pointer before dereferencing */
1057 prv = pdev_id->data;
1058 if (!prv)
1059 continue;
1060
1061 altr_init_a10_ecc_block(child, BIT(irq),
1062 prv->ecc_enable_mask, 0);
1063 }
1064
1065 of_node_put(np);
1066 return 0;
1067 }
1068
1069 /*********************** OCRAM EDAC Device Functions *********************/
1070
1071 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1072
1073 static void *ocram_alloc_mem(size_t size, void **other)
1074 {
1075 struct device_node *np;
1076 struct gen_pool *gp;
1077 void *sram_addr;
1078
1079 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc");
1080 if (!np)
1081 return NULL;
1082
1083 gp = of_gen_pool_get(np, "iram", 0);
1084 of_node_put(np);
1085 if (!gp)
1086 return NULL;
1087
1088 sram_addr = (void *)gen_pool_alloc(gp, size);
1089 if (!sram_addr)
1090 return NULL;
1091
1092 memset(sram_addr, 0, size);
1093 /* Ensure data is written out */
1094 wmb();
1095
1096 /* Remember this handle for freeing later */
1097 *other = gp;
1098
1099 return sram_addr;
1100 }
1101
1102 static void ocram_free_mem(void *p, size_t size, void *other)
1103 {
1104 gen_pool_free((struct gen_pool *)other, (u32)p, size);
1105 }
1106
1107 static const struct edac_device_prv_data ocramecc_data = {
1108 .setup = altr_check_ecc_deps,
1109 .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),
1110 .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR),
1111 .dbgfs_name = "altr_ocram_trigger",
1112 .alloc_mem = ocram_alloc_mem,
1113 .free_mem = ocram_free_mem,
1114 .ecc_enable_mask = ALTR_OCR_ECC_EN,
1115 .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET,
1116 .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS),
1117 .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD),
1118 .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET,
1119 .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE,
1120 .inject_fops = &altr_edac_device_inject_fops,
1121 };
1122
1123 static const struct edac_device_prv_data a10_ocramecc_data = {
1124 .setup = altr_check_ecc_deps,
1125 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1126 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1127 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM,
1128 .dbgfs_name = "altr_ocram_trigger",
1129 .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL,
1130 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1131 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1132 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1133 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1134 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1135 .inject_fops = &altr_edac_a10_device_inject_fops,
1136 /*
1137 * OCRAM panic on uncorrectable error because sleep/resume
1138 * functions and FPGA contents are stored in OCRAM. Prefer
1139 * a kernel panic over executing/loading corrupted data.
1140 */
1141 .panic = true,
1142 };
1143
1144 #endif /* CONFIG_EDAC_ALTERA_OCRAM */
1145
1146 /********************* L2 Cache EDAC Device Functions ********************/
1147
1148 #ifdef CONFIG_EDAC_ALTERA_L2C
1149
1150 static void *l2_alloc_mem(size_t size, void **other)
1151 {
1152 struct device *dev = *other;
1153 void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL);
1154
1155 if (!ptemp)
1156 return NULL;
1157
1158 /* Make sure everything is written out */
1159 wmb();
1160
1161 /*
1162 * Clean all cache levels up to LoC (includes L2)
1163 * This ensures the corrupted data is written into
1164 * L2 cache for readback test (which causes ECC error).
1165 */
1166 flush_cache_all();
1167
1168 return ptemp;
1169 }
1170
1171 static void l2_free_mem(void *p, size_t size, void *other)
1172 {
1173 struct device *dev = other;
1174
1175 if (dev && p)
1176 devm_kfree(dev, p);
1177 }
1178
1179 /*
1180 * altr_l2_check_deps()
1181 * Test for L2 cache ECC dependencies upon entry because
1182 * platform specific startup should have initialized the L2
1183 * memory and enabled the ECC.
1184 * Bail if ECC is not enabled.
1185 * Note that L2 Cache Enable is forced at build time.
1186 */
1187 static int altr_l2_check_deps(struct altr_edac_device_dev *device)
1188 {
1189 void __iomem *base = device->base;
1190 const struct edac_device_prv_data *prv = device->data;
1191
1192 if ((readl(base) & prv->ecc_enable_mask) ==
1193 prv->ecc_enable_mask)
1194 return 0;
1195
1196 edac_printk(KERN_ERR, EDAC_DEVICE,
1197 "L2: No ECC present, or ECC disabled\n");
1198 return -ENODEV;
1199 }
1200
1201 static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id)
1202 {
1203 struct altr_edac_device_dev *dci = dev_id;
1204
1205 if (irq == dci->sb_irq) {
1206 regmap_write(dci->edac->ecc_mgr_map,
1207 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1208 A10_SYSGMR_MPU_CLEAR_L2_ECC_SB);
1209 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
1210
1211 return IRQ_HANDLED;
1212 } else if (irq == dci->db_irq) {
1213 regmap_write(dci->edac->ecc_mgr_map,
1214 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1215 A10_SYSGMR_MPU_CLEAR_L2_ECC_MB);
1216 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
1217 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
1218
1219 return IRQ_HANDLED;
1220 }
1221
1222 WARN_ON(1);
1223
1224 return IRQ_NONE;
1225 }
1226
1227 static const struct edac_device_prv_data l2ecc_data = {
1228 .setup = altr_l2_check_deps,
1229 .ce_clear_mask = 0,
1230 .ue_clear_mask = 0,
1231 .dbgfs_name = "altr_l2_trigger",
1232 .alloc_mem = l2_alloc_mem,
1233 .free_mem = l2_free_mem,
1234 .ecc_enable_mask = ALTR_L2_ECC_EN,
1235 .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS),
1236 .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD),
1237 .set_err_ofst = ALTR_L2_ECC_REG_OFFSET,
1238 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1239 .inject_fops = &altr_edac_device_inject_fops,
1240 };
1241
1242 static const struct edac_device_prv_data a10_l2ecc_data = {
1243 .setup = altr_l2_check_deps,
1244 .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR,
1245 .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR,
1246 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2,
1247 .dbgfs_name = "altr_l2_trigger",
1248 .alloc_mem = l2_alloc_mem,
1249 .free_mem = l2_free_mem,
1250 .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL,
1251 .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK,
1252 .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK,
1253 .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST,
1254 .ecc_irq_handler = altr_edac_a10_l2_irq,
1255 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1256 .inject_fops = &altr_edac_device_inject_fops,
1257 };
1258
1259 #endif /* CONFIG_EDAC_ALTERA_L2C */
1260
1261 /********************* Ethernet Device Functions ********************/
1262
1263 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1264
1265 static const struct edac_device_prv_data a10_enetecc_data = {
1266 .setup = altr_check_ecc_deps,
1267 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1268 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1269 .dbgfs_name = "altr_trigger",
1270 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1271 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1272 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1273 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1274 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1275 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1276 .inject_fops = &altr_edac_a10_device_inject_fops,
1277 };
1278
1279 static int __init socfpga_init_ethernet_ecc(void)
1280 {
1281 return altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");
1282 }
1283
1284 early_initcall(socfpga_init_ethernet_ecc);
1285
1286 #endif /* CONFIG_EDAC_ALTERA_ETHERNET */
1287
1288 /********************* Arria10 EDAC Device Functions *************************/
1289 static const struct of_device_id altr_edac_a10_device_of_match[] = {
1290 #ifdef CONFIG_EDAC_ALTERA_L2C
1291 { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data },
1292 #endif
1293 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1294 { .compatible = "altr,socfpga-a10-ocram-ecc",
1295 .data = &a10_ocramecc_data },
1296 #endif
1297 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1298 { .compatible = "altr,socfpga-eth-mac-ecc",
1299 .data = &a10_enetecc_data },
1300 #endif
1301 {},
1302 };
1303 MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);
1304
1305 /*
1306 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
1307 * because 2 IRQs are shared among the all ECC peripherals. The ECC
1308 * manager manages the IRQs and the children.
1309 * Based on xgene_edac.c peripheral code.
1310 */
1311
1312 static ssize_t altr_edac_a10_device_trig(struct file *file,
1313 const char __user *user_buf,
1314 size_t count, loff_t *ppos)
1315 {
1316 struct edac_device_ctl_info *edac_dci = file->private_data;
1317 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1318 const struct edac_device_prv_data *priv = drvdata->data;
1319 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1320 unsigned long flags;
1321 u8 trig_type;
1322
1323 if (!user_buf || get_user(trig_type, user_buf))
1324 return -EFAULT;
1325
1326 local_irq_save(flags);
1327 if (trig_type == ALTR_UE_TRIGGER_CHAR)
1328 writel(priv->ue_set_mask, set_addr);
1329 else
1330 writel(priv->ce_set_mask, set_addr);
1331 /* Ensure the interrupt test bits are set */
1332 wmb();
1333 local_irq_restore(flags);
1334
1335 return count;
1336 }
1337
1338 static void altr_edac_a10_irq_handler(struct irq_desc *desc)
1339 {
1340 int dberr, bit, sm_offset, irq_status;
1341 struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc);
1342 struct irq_chip *chip = irq_desc_get_chip(desc);
1343 int irq = irq_desc_get_irq(desc);
1344
1345 dberr = (irq == edac->db_irq) ? 1 : 0;
1346 sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST :
1347 A10_SYSMGR_ECC_INTSTAT_SERR_OFST;
1348
1349 chained_irq_enter(chip, desc);
1350
1351 regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status);
1352
1353 for_each_set_bit(bit, (unsigned long *)&irq_status, 32) {
1354 irq = irq_linear_revmap(edac->domain, dberr * 32 + bit);
1355 if (irq)
1356 generic_handle_irq(irq);
1357 }
1358
1359 chained_irq_exit(chip, desc);
1360 }
1361
1362 static int validate_parent_available(struct device_node *np)
1363 {
1364 struct device_node *parent;
1365 int ret = 0;
1366
1367 /* Ensure parent device is enabled if parent node exists */
1368 parent = of_parse_phandle(np, "altr,ecc-parent", 0);
1369 if (parent && !of_device_is_available(parent))
1370 ret = -ENODEV;
1371
1372 of_node_put(parent);
1373 return ret;
1374 }
1375
1376 static int altr_edac_a10_device_add(struct altr_arria10_edac *edac,
1377 struct device_node *np)
1378 {
1379 struct edac_device_ctl_info *dci;
1380 struct altr_edac_device_dev *altdev;
1381 char *ecc_name = (char *)np->name;
1382 struct resource res;
1383 int edac_idx;
1384 int rc = 0;
1385 const struct edac_device_prv_data *prv;
1386 /* Get matching node and check for valid result */
1387 const struct of_device_id *pdev_id =
1388 of_match_node(altr_edac_a10_device_of_match, np);
1389 if (IS_ERR_OR_NULL(pdev_id))
1390 return -ENODEV;
1391
1392 /* Get driver specific data for this EDAC device */
1393 prv = pdev_id->data;
1394 if (IS_ERR_OR_NULL(prv))
1395 return -ENODEV;
1396
1397 if (validate_parent_available(np))
1398 return -ENODEV;
1399
1400 if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL))
1401 return -ENOMEM;
1402
1403 rc = of_address_to_resource(np, 0, &res);
1404 if (rc < 0) {
1405 edac_printk(KERN_ERR, EDAC_DEVICE,
1406 "%s: no resource address\n", ecc_name);
1407 goto err_release_group;
1408 }
1409
1410 edac_idx = edac_device_alloc_index();
1411 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name,
1412 1, ecc_name, 1, 0, NULL, 0,
1413 edac_idx);
1414
1415 if (!dci) {
1416 edac_printk(KERN_ERR, EDAC_DEVICE,
1417 "%s: Unable to allocate EDAC device\n", ecc_name);
1418 rc = -ENOMEM;
1419 goto err_release_group;
1420 }
1421
1422 altdev = dci->pvt_info;
1423 dci->dev = edac->dev;
1424 altdev->edac_dev_name = ecc_name;
1425 altdev->edac_idx = edac_idx;
1426 altdev->edac = edac;
1427 altdev->edac_dev = dci;
1428 altdev->data = prv;
1429 altdev->ddev = *edac->dev;
1430 dci->dev = &altdev->ddev;
1431 dci->ctl_name = "Altera ECC Manager";
1432 dci->mod_name = ecc_name;
1433 dci->dev_name = ecc_name;
1434
1435 altdev->base = devm_ioremap_resource(edac->dev, &res);
1436 if (IS_ERR(altdev->base)) {
1437 rc = PTR_ERR(altdev->base);
1438 goto err_release_group1;
1439 }
1440
1441 /* Check specific dependencies for the module */
1442 if (altdev->data->setup) {
1443 rc = altdev->data->setup(altdev);
1444 if (rc)
1445 goto err_release_group1;
1446 }
1447
1448 altdev->sb_irq = irq_of_parse_and_map(np, 0);
1449 if (!altdev->sb_irq) {
1450 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n");
1451 rc = -ENODEV;
1452 goto err_release_group1;
1453 }
1454 rc = devm_request_irq(edac->dev, altdev->sb_irq,
1455 prv->ecc_irq_handler,
1456 IRQF_SHARED, ecc_name, altdev);
1457 if (rc) {
1458 edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n");
1459 goto err_release_group1;
1460 }
1461
1462 altdev->db_irq = irq_of_parse_and_map(np, 1);
1463 if (!altdev->db_irq) {
1464 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n");
1465 rc = -ENODEV;
1466 goto err_release_group1;
1467 }
1468 rc = devm_request_irq(edac->dev, altdev->db_irq,
1469 prv->ecc_irq_handler,
1470 IRQF_SHARED, ecc_name, altdev);
1471 if (rc) {
1472 edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n");
1473 goto err_release_group1;
1474 }
1475
1476 rc = edac_device_add_device(dci);
1477 if (rc) {
1478 dev_err(edac->dev, "edac_device_add_device failed\n");
1479 rc = -ENOMEM;
1480 goto err_release_group1;
1481 }
1482
1483 altr_create_edacdev_dbgfs(dci, prv);
1484
1485 list_add(&altdev->next, &edac->a10_ecc_devices);
1486
1487 devres_remove_group(edac->dev, altr_edac_a10_device_add);
1488
1489 return 0;
1490
1491 err_release_group1:
1492 edac_device_free_ctl_info(dci);
1493 err_release_group:
1494 devres_release_group(edac->dev, NULL);
1495 edac_printk(KERN_ERR, EDAC_DEVICE,
1496 "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1497
1498 return rc;
1499 }
1500
1501 static void a10_eccmgr_irq_mask(struct irq_data *d)
1502 {
1503 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
1504
1505 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST,
1506 BIT(d->hwirq));
1507 }
1508
1509 static void a10_eccmgr_irq_unmask(struct irq_data *d)
1510 {
1511 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
1512
1513 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST,
1514 BIT(d->hwirq));
1515 }
1516
1517 static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq,
1518 irq_hw_number_t hwirq)
1519 {
1520 struct altr_arria10_edac *edac = d->host_data;
1521
1522 irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq);
1523 irq_set_chip_data(irq, edac);
1524 irq_set_noprobe(irq);
1525
1526 return 0;
1527 }
1528
1529 struct irq_domain_ops a10_eccmgr_ic_ops = {
1530 .map = a10_eccmgr_irqdomain_map,
1531 .xlate = irq_domain_xlate_twocell,
1532 };
1533
1534 static int altr_edac_a10_probe(struct platform_device *pdev)
1535 {
1536 struct altr_arria10_edac *edac;
1537 struct device_node *child;
1538
1539 edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);
1540 if (!edac)
1541 return -ENOMEM;
1542
1543 edac->dev = &pdev->dev;
1544 platform_set_drvdata(pdev, edac);
1545 INIT_LIST_HEAD(&edac->a10_ecc_devices);
1546
1547 edac->ecc_mgr_map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1548 "altr,sysmgr-syscon");
1549 if (IS_ERR(edac->ecc_mgr_map)) {
1550 edac_printk(KERN_ERR, EDAC_DEVICE,
1551 "Unable to get syscon altr,sysmgr-syscon\n");
1552 return PTR_ERR(edac->ecc_mgr_map);
1553 }
1554
1555 edac->irq_chip.name = pdev->dev.of_node->name;
1556 edac->irq_chip.irq_mask = a10_eccmgr_irq_mask;
1557 edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask;
1558 edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64,
1559 &a10_eccmgr_ic_ops, edac);
1560 if (!edac->domain) {
1561 dev_err(&pdev->dev, "Error adding IRQ domain\n");
1562 return -ENOMEM;
1563 }
1564
1565 edac->sb_irq = platform_get_irq(pdev, 0);
1566 if (edac->sb_irq < 0) {
1567 dev_err(&pdev->dev, "No SBERR IRQ resource\n");
1568 return edac->sb_irq;
1569 }
1570
1571 irq_set_chained_handler_and_data(edac->sb_irq,
1572 altr_edac_a10_irq_handler,
1573 edac);
1574
1575 edac->db_irq = platform_get_irq(pdev, 1);
1576 if (edac->db_irq < 0) {
1577 dev_err(&pdev->dev, "No DBERR IRQ resource\n");
1578 return edac->db_irq;
1579 }
1580 irq_set_chained_handler_and_data(edac->db_irq,
1581 altr_edac_a10_irq_handler,
1582 edac);
1583
1584 for_each_child_of_node(pdev->dev.of_node, child) {
1585 if (!of_device_is_available(child))
1586 continue;
1587 if (of_device_is_compatible(child, "altr,socfpga-a10-l2-ecc"))
1588 altr_edac_a10_device_add(edac, child);
1589 else if ((of_device_is_compatible(child,
1590 "altr,socfpga-a10-ocram-ecc")) ||
1591 (of_device_is_compatible(child,
1592 "altr,socfpga-eth-mac-ecc")))
1593 altr_edac_a10_device_add(edac, child);
1594 else if (of_device_is_compatible(child,
1595 "altr,sdram-edac-a10"))
1596 of_platform_populate(pdev->dev.of_node,
1597 altr_sdram_ctrl_of_match,
1598 NULL, &pdev->dev);
1599 }
1600
1601 return 0;
1602 }
1603
1604 static const struct of_device_id altr_edac_a10_of_match[] = {
1605 { .compatible = "altr,socfpga-a10-ecc-manager" },
1606 {},
1607 };
1608 MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match);
1609
1610 static struct platform_driver altr_edac_a10_driver = {
1611 .probe = altr_edac_a10_probe,
1612 .driver = {
1613 .name = "socfpga_a10_ecc_manager",
1614 .of_match_table = altr_edac_a10_of_match,
1615 },
1616 };
1617 module_platform_driver(altr_edac_a10_driver);
1618
1619 MODULE_LICENSE("GPL v2");
1620 MODULE_AUTHOR("Thor Thayer");
1621 MODULE_DESCRIPTION("EDAC Driver for Altera Memories");
Linux with added FPC-III support