Documentation/ABI/testing/sysfs-bus-coresight-devices-stm

   1 What:           /sys/bus/coresight/devices/<memory_map>.stm/enable_source
   2 Date:           April 2016
   3 KernelVersion:  4.7
   4 Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
   5 Description:    (RW) Enable/disable tracing on this specific trace macrocell.
   6                 Enabling the trace macrocell implies it has been configured
   7                 properly and a sink has been identified for it.  The path
   8                 of coresight components linking the source to the sink is
   9                 configured and managed automatically by the coresight framework.
  10
  11 What:           /sys/bus/coresight/devices/<memory_map>.stm/hwevent_enable
  12 Date:           April 2016
  13 KernelVersion:  4.7
  14 Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
  15 Description:    (RW) Provides access to the HW event enable register, used in
  16                 conjunction with HW event bank select register.
  17
  18 What:           /sys/bus/coresight/devices/<memory_map>.stm/hwevent_select
  19 Date:           April 2016
  20 KernelVersion:  4.7
  21 Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
  22 Description:    (RW) Gives access to the HW event block select register
  23                 (STMHEBSR) in order to configure up to 256 channels.  Used in
  24                 conjunction with "hwevent_enable" register as described above.
  25
  26 What:           /sys/bus/coresight/devices/<memory_map>.stm/port_enable
  27 Date:           April 2016
  28 KernelVersion:  4.7
  29 Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
  30 Description:    (RW) Provides access to the stimulus port enable register
  31                 (STMSPER).  Used in conjunction with "port_select" described
  32                 below.
  33
  34 What:           /sys/bus/coresight/devices/<memory_map>.stm/port_select
  35 Date:           April 2016
  36 KernelVersion:  4.7
  37 Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
  38 Description:    (RW) Used to determine which bank of stimulus port bit in
  39                 register STMSPER (see above) apply to.
  40
  41 What:           /sys/bus/coresight/devices/<memory_map>.stm/status
  42 Date:           April 2016
  43 KernelVersion:  4.7
  44 Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
  45 Description:    (R) List various control and status registers.  The specific
  46                 layout and content is driver specific.
  47
  48 What:           /sys/bus/coresight/devices/<memory_map>.stm/traceid
  49 Date:           April 2016
  50 KernelVersion:  4.7
  51 Contact:        Mathieu Poirier <mathieu.poirier@linaro.org>
  52 Description:    (RW) Holds the trace ID that will appear in the trace stream
  53                 coming from this trace entity.