drm/i915/dsi: Control panel and backlight enable GPIOs on BYT
[linux/fpc-iii.git] / drivers / gpu / drm / i915 / display / intel_dsi.h
blob7481a5aa3084692ee012fbb5def21ce6907217c6
1 /*
2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #ifndef _INTEL_DSI_H
25 #define _INTEL_DSI_H
27 #include <drm/drm_crtc.h>
28 #include <drm/drm_mipi_dsi.h>
30 #include "intel_display_types.h"
32 #define INTEL_DSI_VIDEO_MODE 0
33 #define INTEL_DSI_COMMAND_MODE 1
35 /* Dual Link support */
36 #define DSI_DUAL_LINK_NONE 0
37 #define DSI_DUAL_LINK_FRONT_BACK 1
38 #define DSI_DUAL_LINK_PIXEL_ALT 2
40 struct intel_dsi_host;
42 struct intel_dsi {
43 struct intel_encoder base;
45 struct intel_dsi_host *dsi_hosts[I915_MAX_PORTS];
46 intel_wakeref_t io_wakeref[I915_MAX_PORTS];
48 /* GPIO Desc for panel and backlight control */
49 struct gpio_desc *gpio_panel;
50 struct gpio_desc *gpio_backlight;
52 struct intel_connector *attached_connector;
54 /* bit mask of ports (vlv dsi) or phys (icl dsi) being driven */
55 union {
56 u16 ports; /* VLV DSI */
57 u16 phys; /* ICL DSI */
60 /* if true, use HS mode, otherwise LP */
61 bool hs;
63 /* virtual channel */
64 int channel;
66 /* Video mode or command mode */
67 u16 operation_mode;
69 /* number of DSI lanes */
70 unsigned int lane_count;
73 * video mode pixel format
75 * XXX: consolidate on .format in struct mipi_dsi_device.
77 enum mipi_dsi_pixel_format pixel_format;
79 /* video mode format for MIPI_VIDEO_MODE_FORMAT register */
80 u32 video_mode_format;
82 /* eot for MIPI_EOT_DISABLE register */
83 u8 eotp_pkt;
84 u8 clock_stop;
86 u8 escape_clk_div;
87 u8 dual_link;
89 u16 dcs_backlight_ports;
90 u16 dcs_cabc_ports;
92 /* RGB or BGR */
93 bool bgr_enabled;
95 u8 pixel_overlap;
96 u32 port_bits;
97 u32 bw_timer;
98 u32 dphy_reg;
100 /* data lanes dphy timing */
101 u32 dphy_data_lane_reg;
102 u32 video_frmt_cfg_bits;
103 u16 lp_byte_clk;
105 /* timeouts in byte clocks */
106 u16 hs_tx_timeout;
107 u16 lp_rx_timeout;
108 u16 turn_arnd_val;
109 u16 rst_timer_val;
110 u16 hs_to_lp_count;
111 u16 clk_lp_to_hs_count;
112 u16 clk_hs_to_lp_count;
114 u16 init_count;
115 u32 pclk;
116 u16 burst_mode_ratio;
118 /* all delays in ms */
119 u16 backlight_off_delay;
120 u16 backlight_on_delay;
121 u16 panel_on_delay;
122 u16 panel_off_delay;
123 u16 panel_pwr_cycle_delay;
126 struct intel_dsi_host {
127 struct mipi_dsi_host base;
128 struct intel_dsi *intel_dsi;
129 enum port port;
131 /* our little hack */
132 struct mipi_dsi_device *device;
135 static inline struct intel_dsi_host *to_intel_dsi_host(struct mipi_dsi_host *h)
137 return container_of(h, struct intel_dsi_host, base);
140 #define for_each_dsi_port(__port, __ports_mask) \
141 for_each_port_masked(__port, __ports_mask)
142 #define for_each_dsi_phy(__phy, __phys_mask) \
143 for_each_phy_masked(__phy, __phys_mask)
145 static inline struct intel_dsi *enc_to_intel_dsi(struct drm_encoder *encoder)
147 return container_of(encoder, struct intel_dsi, base.base);
150 static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
152 return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
155 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
157 return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
160 static inline u16 intel_dsi_encoder_ports(struct intel_encoder *encoder)
162 return enc_to_intel_dsi(&encoder->base)->ports;
165 /* icl_dsi.c */
166 void icl_dsi_init(struct drm_i915_private *dev_priv);
168 /* intel_dsi.c */
169 int intel_dsi_bitrate(const struct intel_dsi *intel_dsi);
170 int intel_dsi_tlpx_ns(const struct intel_dsi *intel_dsi);
171 enum drm_panel_orientation
172 intel_dsi_get_panel_orientation(struct intel_connector *connector);
174 /* vlv_dsi.c */
175 void vlv_dsi_wait_for_fifo_empty(struct intel_dsi *intel_dsi, enum port port);
176 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt);
177 int intel_dsi_get_modes(struct drm_connector *connector);
178 enum drm_mode_status intel_dsi_mode_valid(struct drm_connector *connector,
179 struct drm_display_mode *mode);
180 struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
181 const struct mipi_dsi_host_ops *funcs,
182 enum port port);
183 void vlv_dsi_init(struct drm_i915_private *dev_priv);
185 /* vlv_dsi_pll.c */
186 int vlv_dsi_pll_compute(struct intel_encoder *encoder,
187 struct intel_crtc_state *config);
188 void vlv_dsi_pll_enable(struct intel_encoder *encoder,
189 const struct intel_crtc_state *config);
190 void vlv_dsi_pll_disable(struct intel_encoder *encoder);
191 u32 vlv_dsi_get_pclk(struct intel_encoder *encoder,
192 struct intel_crtc_state *config);
193 void vlv_dsi_reset_clocks(struct intel_encoder *encoder, enum port port);
195 bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv);
196 int bxt_dsi_pll_compute(struct intel_encoder *encoder,
197 struct intel_crtc_state *config);
198 void bxt_dsi_pll_enable(struct intel_encoder *encoder,
199 const struct intel_crtc_state *config);
200 void bxt_dsi_pll_disable(struct intel_encoder *encoder);
201 u32 bxt_dsi_get_pclk(struct intel_encoder *encoder,
202 struct intel_crtc_state *config);
203 void bxt_dsi_reset_clocks(struct intel_encoder *encoder, enum port port);
205 /* intel_dsi_vbt.c */
206 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id);
207 void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on);
208 void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi);
209 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi,
210 enum mipi_seq seq_id);
211 void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec);
212 void intel_dsi_log_params(struct intel_dsi *intel_dsi);
214 #endif /* _INTEL_DSI_H */