Documentation/devicetree/bindings/arm/coresight.txt

   1 * CoreSight Components:
   2
   3 CoreSight components are compliant with the ARM CoreSight architecture
   4 specification and can be connected in various topologies to suit a particular
   5 SoCs tracing needs. These trace components can generally be classified as
   6 sinks, links and sources. Trace data produced by one or more sources flows
   7 through the intermediate links connecting the source to the currently selected
   8 sink. Each CoreSight component device should use these properties to describe
   9 its hardware characteristcs.
  10
  11 * Required properties for all components *except* non-configurable replicators
  12   and non-configurable funnels:
  13
  14         * compatible: These have to be supplemented with "arm,primecell" as
  15           drivers are using the AMBA bus interface.  Possible values include:
  16                 - Embedded Trace Buffer (version 1.0):
  17                         "arm,coresight-etb10", "arm,primecell";
  18
  19                 - Trace Port Interface Unit:
  20                         "arm,coresight-tpiu", "arm,primecell";
  21
  22                 - Trace Memory Controller, used for Embedded Trace Buffer(ETB),
  23                   Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR)
  24                   configuration.  The configuration mode (ETB, ETF, ETR) is
  25                   discovered at boot time when the device is probed.
  26                         "arm,coresight-tmc", "arm,primecell";
  27
  28                 - Trace Programmable Funnel:
  29                         "arm,coresight-dynamic-funnel", "arm,primecell";
  30                         "arm,coresight-funnel", "arm,primecell"; (OBSOLETE. For
  31                                 backward compatibility and will be removed)
  32
  33                 - Embedded Trace Macrocell (version 3.x) and
  34                                         Program Flow Trace Macrocell:
  35                         "arm,coresight-etm3x", "arm,primecell";
  36
  37                 - Embedded Trace Macrocell (version 4.x):
  38                         "arm,coresight-etm4x", "arm,primecell";
  39
  40                 - Coresight programmable Replicator :
  41                         "arm,coresight-dynamic-replicator", "arm,primecell";
  42
  43                 - System Trace Macrocell:
  44                         "arm,coresight-stm", "arm,primecell"; [1]
  45                 - Coresight Address Translation Unit (CATU)
  46                         "arm,coresight-catu", "arm,primecell";
  47
  48                 - Coresight Cross Trigger Interface (CTI):
  49                         "arm,coresight-cti", "arm,primecell";
  50                         See coresight-cti.yaml for full CTI definitions.
  51
  52         * reg: physical base address and length of the register
  53           set(s) of the component.
  54
  55         * clocks: the clocks associated to this component.
  56
  57         * clock-names: the name of the clocks referenced by the code.
  58           Since we are using the AMBA framework, the name of the clock
  59           providing the interconnect should be "apb_pclk", and some
  60           coresight blocks also have an additional clock "atclk", which
  61           clocks the core of that coresight component. The latter clock
  62           is optional.
  63
  64         * port or ports: see "Graph bindings for Coresight" below.
  65
  66 * Additional required property for Embedded Trace Macrocell (version 3.x and
  67   version 4.x):
  68         * cpu: the cpu phandle this ETM/PTM is affined to. Do not
  69           assume it to default to CPU0 if omitted.
  70
  71 * Additional required properties for System Trace Macrocells (STM):
  72         * reg: along with the physical base address and length of the register
  73           set as described above, another entry is required to describe the
  74           mapping of the extended stimulus port area.
  75
  76         * reg-names: the only acceptable values are "stm-base" and
  77           "stm-stimulus-base", each corresponding to the areas defined in "reg".
  78
  79 * Required properties for Coresight Cross Trigger Interface (CTI)
  80         See coresight-cti.yaml for full CTI definitions.
  81
  82 * Required properties for devices that don't show up on the AMBA bus, such as
  83   non-configurable replicators and non-configurable funnels:
  84
  85         * compatible: Currently supported value is (note the absence of the
  86           AMBA markee):
  87                 - Coresight Non-configurable Replicator:
  88                         "arm,coresight-static-replicator";
  89                         "arm,coresight-replicator"; (OBSOLETE. For backward
  90                                 compatibility and will be removed)
  91
  92                 - Coresight Non-configurable Funnel:
  93                         "arm,coresight-static-funnel";
  94
  95         * port or ports: see "Graph bindings for Coresight" below.
  96
  97 * Optional properties for all components:
  98
  99         * arm,coresight-loses-context-with-cpu : boolean. Indicates that the
 100           hardware will lose register context on CPU power down (e.g. CPUIdle).
 101           An example of where this may be needed are systems which contain a
 102           coresight component and CPU in the same power domain. When the CPU
 103           powers down the coresight component also powers down and loses its
 104           context. This property is currently only used for the ETM 4.x driver.
 105
 106 * Optional properties for ETM/PTMs:
 107
 108         * arm,cp14: must be present if the system accesses ETM/PTM management
 109           registers via co-processor 14.
 110
 111         * qcom,skip-power-up: boolean. Indicates that an implementation can
 112           skip powering up the trace unit. TRCPDCR.PU does not have to be set
 113           on Qualcomm Technologies Inc. systems since ETMs are in the same power
 114           domain as their CPU cores. This property is required to identify such
 115           systems with hardware errata where the CPU watchdog counter is stopped
 116           when TRCPDCR.PU is set.
 117
 118 * Optional property for TMC:
 119
 120         * arm,buffer-size: size of contiguous buffer space for TMC ETR
 121           (embedded trace router). This property is obsolete. The buffer size
 122           can be configured dynamically via buffer_size property in sysfs.
 123
 124         * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
 125           use the SG mode on this system.
 126
 127 * Optional property for CATU :
 128         * interrupts : Exactly one SPI may be listed for reporting the address
 129           error
 130
 131 * Optional property for configurable replicators:
 132
 133         * qcom,replicator-loses-context: boolean. Indicates that the replicator
 134           will lose register context when AMBA clock is removed which is observed
 135           in some replicator designs.
 136
 137 Graph bindings for Coresight
 138 -------------------------------
 139
 140 Coresight components are interconnected to create a data path for the flow of
 141 trace data generated from the "sources" to their collection points "sink".
 142 Each coresight component must describe the "input" and "output" connections.
 143 The connections must be described via generic DT graph bindings as described
 144 by the "bindings/graph.txt", where each "port" along with an "endpoint"
 145 component represents a hardware port and the connection.
 146
 147  * All output ports must be listed inside a child node named "out-ports"
 148  * All input ports must be listed inside a child node named "in-ports".
 149  * Port address must match the hardware port number.
 150
 151 Example:
 152
 153 1. Sinks
 154         etb@20010000 {
 155                 compatible = "arm,coresight-etb10", "arm,primecell";
 156                 reg = <0 0x20010000 0 0x1000>;
 157
 158                 clocks = <&oscclk6a>;
 159                 clock-names = "apb_pclk";
 160                 in-ports {
 161                         port {
 162                                 etb_in_port: endpoint@0 {
 163                                         remote-endpoint = <&replicator_out_port0>;
 164                                 };
 165                         };
 166                 };
 167         };
 168
 169         tpiu@20030000 {
 170                 compatible = "arm,coresight-tpiu", "arm,primecell";
 171                 reg = <0 0x20030000 0 0x1000>;
 172
 173                 clocks = <&oscclk6a>;
 174                 clock-names = "apb_pclk";
 175                 in-ports {
 176                         port {
 177                                 tpiu_in_port: endpoint@0 {
 178                                         remote-endpoint = <&replicator_out_port1>;
 179                                 };
 180                         };
 181                 };
 182         };
 183
 184         etr@20070000 {
 185                 compatible = "arm,coresight-tmc", "arm,primecell";
 186                 reg = <0 0x20070000 0 0x1000>;
 187
 188                 clocks = <&oscclk6a>;
 189                 clock-names = "apb_pclk";
 190                 in-ports {
 191                         port {
 192                                 etr_in_port: endpoint {
 193                                         remote-endpoint = <&replicator2_out_port0>;
 194                                 };
 195                         };
 196                 };
 197
 198                 out-ports {
 199                         port {
 200                                 etr_out_port: endpoint {
 201                                         remote-endpoint = <&catu_in_port>;
 202                                 };
 203                         };
 204                 };
 205         };
 206
 207 2. Links
 208         replicator {
 209                 /* non-configurable replicators don't show up on the
 210                  * AMBA bus.  As such no need to add "arm,primecell".
 211                  */
 212                 compatible = "arm,coresight-static-replicator";
 213
 214                 out-ports {
 215                         #address-cells = <1>;
 216                         #size-cells = <0>;
 217
 218                         /* replicator output ports */
 219                         port@0 {
 220                                 reg = <0>;
 221                                 replicator_out_port0: endpoint {
 222                                         remote-endpoint = <&etb_in_port>;
 223                                 };
 224                         };
 225
 226                         port@1 {
 227                                 reg = <1>;
 228                                 replicator_out_port1: endpoint {
 229                                         remote-endpoint = <&tpiu_in_port>;
 230                                 };
 231                         };
 232                 };
 233
 234                 in-ports {
 235                         port {
 236                                 replicator_in_port0: endpoint {
 237                                         remote-endpoint = <&funnel_out_port0>;
 238                                 };
 239                         };
 240                 };
 241         };
 242
 243         funnel {
 244                 /*
 245                  * non-configurable funnel don't show up on the AMBA
 246                  * bus.  As such no need to add "arm,primecell".
 247                  */
 248                 compatible = "arm,coresight-static-funnel";
 249                 clocks = <&crg_ctrl HI3660_PCLK>;
 250                 clock-names = "apb_pclk";
 251
 252                 out-ports {
 253                         port {
 254                                 combo_funnel_out: endpoint {
 255                                         remote-endpoint = <&top_funnel_in>;
 256                                 };
 257                         };
 258                 };
 259
 260                 in-ports {
 261                         #address-cells = <1>;
 262                         #size-cells = <0>;
 263
 264                         port@0 {
 265                                 reg = <0>;
 266                                 combo_funnel_in0: endpoint {
 267                                         remote-endpoint = <&cluster0_etf_out>;
 268                                 };
 269                         };
 270
 271                         port@1 {
 272                                 reg = <1>;
 273                                 combo_funnel_in1: endpoint {
 274                                         remote-endpoint = <&cluster1_etf_out>;
 275                                 };
 276                         };
 277                 };
 278         };
 279
 280         funnel@20040000 {
 281                 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 282                 reg = <0 0x20040000 0 0x1000>;
 283
 284                 clocks = <&oscclk6a>;
 285                 clock-names = "apb_pclk";
 286                 out-ports {
 287                         port {
 288                                 funnel_out_port0: endpoint {
 289                                         remote-endpoint =
 290                                                         <&replicator_in_port0>;
 291                                 };
 292                         };
 293                 };
 294
 295                 in-ports {
 296                         #address-cells = <1>;
 297                         #size-cells = <0>;
 298
 299                         port@0 {
 300                                 reg = <0>;
 301                                 funnel_in_port0: endpoint {
 302                                         remote-endpoint = <&ptm0_out_port>;
 303                                 };
 304                         };
 305
 306                         port@1 {
 307                                 reg = <1>;
 308                                 funnel_in_port1: endpoint {
 309                                         remote-endpoint = <&ptm1_out_port>;
 310                                 };
 311                         };
 312
 313                         port@2 {
 314                                 reg = <2>;
 315                                 funnel_in_port2: endpoint {
 316                                         remote-endpoint = <&etm0_out_port>;
 317                                 };
 318                         };
 319
 320                 };
 321         };
 322
 323 3. Sources
 324         ptm@2201c000 {
 325                 compatible = "arm,coresight-etm3x", "arm,primecell";
 326                 reg = <0 0x2201c000 0 0x1000>;
 327
 328                 cpu = <&cpu0>;
 329                 clocks = <&oscclk6a>;
 330                 clock-names = "apb_pclk";
 331                 out-ports {
 332                         port {
 333                                 ptm0_out_port: endpoint {
 334                                         remote-endpoint = <&funnel_in_port0>;
 335                                 };
 336                         };
 337                 };
 338         };
 339
 340         ptm@2201d000 {
 341                 compatible = "arm,coresight-etm3x", "arm,primecell";
 342                 reg = <0 0x2201d000 0 0x1000>;
 343
 344                 cpu = <&cpu1>;
 345                 clocks = <&oscclk6a>;
 346                 clock-names = "apb_pclk";
 347                 out-ports {
 348                         port {
 349                                 ptm1_out_port: endpoint {
 350                                         remote-endpoint = <&funnel_in_port1>;
 351                                 };
 352                         };
 353                 };
 354         };
 355
 356 4. STM
 357         stm@20100000 {
 358                 compatible = "arm,coresight-stm", "arm,primecell";
 359                 reg = <0 0x20100000 0 0x1000>,
 360                       <0 0x28000000 0 0x180000>;
 361                 reg-names = "stm-base", "stm-stimulus-base";
 362
 363                 clocks = <&soc_smc50mhz>;
 364                 clock-names = "apb_pclk";
 365                 out-ports {
 366                         port {
 367                                 stm_out_port: endpoint {
 368                                         remote-endpoint = <&main_funnel_in_port2>;
 369                                 };
 370                         };
 371                 };
 372         };
 373
 374 5. CATU
 375
 376         catu@207e0000 {
 377                 compatible = "arm,coresight-catu", "arm,primecell";
 378                 reg = <0 0x207e0000 0 0x1000>;
 379
 380                 clocks = <&oscclk6a>;
 381                 clock-names = "apb_pclk";
 382
 383                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 384                 in-ports {
 385                         port {
 386                                 catu_in_port: endpoint {
 387                                         remote-endpoint = <&etr_out_port>;
 388                                 };
 389                         };
 390                 };
 391         };
 392
 393 [1]. There is currently two version of STM: STM32 and STM500.  Both
 394 have the same HW interface and as such don't need an explicit binding name.