4 The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.
7 - compatible: should be set to "cdns,dsi".
8 - reg: physical base address and length of the controller's registers.
9 - interrupts: interrupt line connected to the DSI bridge.
10 - clocks: DSI bridge clocks.
11 - clock-names: must contain "dsi_p_clk" and "dsi_sys_clk".
12 - phys: phandle link to the MIPI D-PHY controller.
13 - phy-names: must contain "dphy".
14 - #address-cells: must be set to 1.
15 - #size-cells: must be set to 0.
18 - resets: DSI reset lines.
19 - reset-names: can contain "dsi_p_rst".
22 - ports: Ports as described in Documentation/devicetree/bindings/graph.txt.
23 2 ports are available:
24 * port 0: this port is only needed if some of your DSI devices are
25 controlled through an external bus like I2C or SPI. Can have at
26 most 4 endpoints. The endpoint number is directly encoding the
27 DSI virtual channel used by this device.
28 * port 1: represents the DPI input.
29 Other ports will be added later to support the new kind of inputs.
31 - one subnode per DSI device connected on the DSI bus. Each DSI device should
32 contain a reg property encoding its virtual channel.
36 compatible = "cdns,dsi";
37 reg = <0x0 0xfd0c0000 0x0 0x1000>;
38 clocks = <&pclk>, <&sysclk>;
39 clock-names = "dsi_p_clk", "dsi_sys_clk";
52 dsi0_dpi_input: endpoint {
53 remote-endpoint = <&xxx_dpi_output>;
59 compatible = "<vendor,panel>";
67 compatible = "cdns,dsi";
68 reg = <0x0 0xfd0c0000 0x0 0x1000>;
69 clocks = <&pclk>, <&sysclk>;
70 clock-names = "dsi_p_clk", "dsi_sys_clk";
86 dsi0_output: endpoint@0 {
88 remote-endpoint = <&dsi_panel_input>;
94 dsi0_dpi_input: endpoint {
95 remote-endpoint = <&xxx_dpi_output>;
103 compatible = "<vendor,panel>";
107 dsi_panel_input: endpoint {
108 remote-endpoint = <&dsi0_output>;