Documentation/devicetree/bindings/dma/mtk-uart-apdma.txt

   1 * Mediatek UART APDMA Controller
   2
   3 Required properties:
   4 - compatible should contain:
   5   * "mediatek,mt2712-uart-dma" for MT2712 compatible APDMA
   6   * "mediatek,mt6577-uart-dma" for MT6577 and all of the above
   7   * "mediatek,mt8516-uart-dma", "mediatek,mt6577" for MT8516 SoC
   8
   9 - reg: The base address of the APDMA register bank.
  10
  11 - interrupts: A single interrupt specifier.
  12  One interrupt per dma-requests, or 8 if no dma-requests property is present
  13
  14 - dma-requests: The number of DMA channels
  15
  16 - clocks : Must contain an entry for each entry in clock-names.
  17   See ../clocks/clock-bindings.txt for details.
  18 - clock-names: The APDMA clock for register accesses
  19
  20 - mediatek,dma-33bits: Present if the DMA requires support
  21
  22 Examples:
  23
  24         apdma: dma-controller@11000400 {
  25                 compatible = "mediatek,mt2712-uart-dma",
  26                              "mediatek,mt6577-uart-dma";
  27                 reg = <0 0x11000400 0 0x80>,
  28                       <0 0x11000480 0 0x80>,
  29                       <0 0x11000500 0 0x80>,
  30                       <0 0x11000580 0 0x80>,
  31                       <0 0x11000600 0 0x80>,
  32                       <0 0x11000680 0 0x80>,
  33                       <0 0x11000700 0 0x80>,
  34                       <0 0x11000780 0 0x80>,
  35                       <0 0x11000800 0 0x80>,
  36                       <0 0x11000880 0 0x80>,
  37                       <0 0x11000900 0 0x80>,
  38                       <0 0x11000980 0 0x80>;
  39                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
  40                              <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
  41                              <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
  42                              <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
  43                              <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
  44                              <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
  45                              <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
  46                              <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
  47                              <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
  48                              <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
  49                              <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
  50                              <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
  51                 dma-requests = <12>;
  52                 clocks = <&pericfg CLK_PERI_AP_DMA>;
  53                 clock-names = "apdma";
  54                 mediatek,dma-33bits;
  55                 #dma-cells = <1>;
  56         };