1 Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager.
2 The ZynqMP SoC uses the PCAP (Processor configuration Port) to configure the
3 Programmable Logic (PL). The configuration uses the firmware interface.
6 - compatible: should contain "xlnx,zynqmp-pcap-fpga"
8 Example for full FPGA configuration:
11 compatible = "fpga-region";
12 fpga-mgr = <&zynqmp_pcap>;
13 #address-cells = <0x1>;
18 zynqmp_firmware: zynqmp-firmware {
19 compatible = "xlnx,zynqmp-firmware";
22 compatible = "xlnx,zynqmp-pcap-fpga";