1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/iio/resolver/adi,ad2s90.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD2S90 Resolver-to-Digital Converter
10 - Matheus Tavares <matheus.bernardino@usp.br>
13 Datasheet: https://www.analog.com/en/products/ad2s90.html
25 Chip's max frequency, as specified in its datasheet, is 2Mhz. But a 600ns
26 delay is expected between the application of a logic LO to CS and the
27 application of SCLK, as also specified. And since the delay is not
28 implemented in the spi code, to satisfy it, SCLK's period should be at
29 most 2 * 600ns, so the max frequency should be 1 / (2 * 6e-7), which gives
36 additionalProperties: false
43 spi-cpol: [ spi-cpha ]
44 spi-cpha: [ spi-cpol ]
53 compatible = "adi,ad2s90";
55 spi-max-frequency = <830000>;