1 Marvell Prestera Switch Chip bindings
2 -------------------------------------
5 - compatible: must be "marvell,prestera" and one of the following
6 "marvell,prestera-98dx3236",
7 "marvell,prestera-98dx3336",
8 "marvell,prestera-98dx4251",
9 - reg: address and length of the register set for the device.
10 - interrupts: interrupt for the device
13 - dfx: phandle reference to the "DFX Server" node
18 compatible = "simple-bus";
21 ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
24 compatible = "marvell,prestera-98dx3236", "marvell,prestera";
26 interrupts = <33>, <34>, <35>;
35 - compatible: must be "marvell,dfx-server", "simple-bus"
36 - ranges: describes the address mapping of a memory-mapped bus.
37 - reg: address and length of the register set for the device.
42 compatible = "marvell,dfx-server", "simple-bus";
45 ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
46 reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
49 Marvell Prestera SwitchDev bindings
50 -----------------------------------
52 - compatible: must be "marvell,prestera"
53 - base-mac-provider: describes handle to node which provides base mac address,
54 might be a static base mac address or nvme cell provider.
58 eeprom_mac_addr: eeprom-mac-addr {
59 compatible = "eeprom,mac-addr-cell";
62 nvmem = <&eeprom_at24>;
66 compatible = "marvell,prestera";
69 base-mac-provider = <&eeprom_mac_addr>;
72 The current implementation of Prestera Switchdev PCI interface driver requires
73 that BAR2 is assigned to 0xf6000000 as base address from the PCI IO range:
76 ranges = <0x81000000 0x0 0xfb000000 0x0 0xfb000000 0x0 0xf0000
77 0x82000000 0x0 0xf6000000 0x0 0xf6000000 0x0 0x2000000
78 0x82000000 0x0 0xf9000000 0x0 0xf9000000 0x0 0x100000>;
79 phys = <&cp0_comphy0 0>;