1 # SPDX-License-Identifier: GPL-2.0+
4 $id: http://devicetree.org/schemas/net/qca,ar803x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Atheros AR803x PHY
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
15 Bindings for Qualcomm Atheros AR803x PHYs
18 - $ref: ethernet-phy.yaml#
21 qca,clk-out-frequency:
22 description: Clock output frequency in Hertz.
23 $ref: /schemas/types.yaml#/definitions/uint32
24 enum: [25000000, 50000000, 62500000, 125000000]
27 description: Clock output driver strength.
28 $ref: /schemas/types.yaml#/definitions/uint32
33 If set, keep the PLL enabled even if there is no link. Useful if you
34 want to use the clock output without an ethernet link.
36 Only supported on the AR8031.
41 RGMII I/O voltage regulator (see regulator/regulator.yaml).
43 The PHY supports RGMII I/O voltages of 1.5V, 1.8V and 2.5V. You can
44 either connect this to the vddio-regulator (1.5V / 1.8V) or the
45 vddh-regulator (2.5V).
47 Only supported on the AR8031.
52 Initial data for the VDDIO regulator. Set this to 1.5V or 1.8V.
53 $ref: /schemas/regulator/regulator.yaml
58 Dummy subnode to model the external connection of the PHY VDDH
60 $ref: /schemas/regulator/regulator.yaml
62 unevaluatedProperties: false
66 #include <dt-bindings/net/qca-ar803x.h>
72 phy-mode = "rgmii-id";
77 qca,clk-out-frequency = <125000000>;
78 qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
80 vddio-supply = <&vddio>;
82 vddio: vddio-regulator {
83 regulator-min-microvolt = <1800000>;
84 regulator-max-microvolt = <1800000>;
89 #include <dt-bindings/net/qca-ar803x.h>
95 phy-mode = "rgmii-id";
100 qca,clk-out-frequency = <50000000>;
101 qca,keep-pll-enabled;
103 vddio-supply = <&vddh>;
105 vddh: vddh-regulator {