1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/qcom,msm8226-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. MSM8226 TLMM block
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 This binding describes the Top Level Mode Multiplexer block found in the
18 const: qcom,msm8226-pinctrl
21 description: Specifies the base address and size of the TLMM register space
25 description: Specifies the TLMM summary IRQ
28 interrupt-controller: true
31 description: Specifies the PIN numbers and Flags, as defined in
32 include/dt-bindings/interrupt-controller/irq.h
38 description: Specifying the pin number and flags, as defined in
39 include/dt-bindings/gpio/gpio.h
48 #PIN CONFIGURATION NODES
53 Pinctrl node's client devices use subnodes for desired pin configuration.
54 Client device subnodes use below standard properties.
55 $ref: "/schemas/pinctrl/pincfg-node.yaml"
60 List of gpio pins affected by the properties specified in this
64 - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$"
65 - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
71 Specify the alternative function to be configured for the specified
72 pins. Functions are only valid for gpio pins.
73 enum: [ gpio, cci_i2c0, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim5,
74 blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c5, blsp_spi1,
75 blsp_spi2, blsp_spi3, blsp_spi5, blsp_uart1, blsp_uart2,
76 blsp_uart3, blsp_uart5, cam_mclk0, cam_mclk1, wlan ]
79 enum: [2, 4, 6, 8, 10, 12, 14, 16]
82 Selects the drive strength for the specified pins, in mA.
98 additionalProperties: false
104 - interrupt-controller
110 additionalProperties: false
114 #include <dt-bindings/interrupt-controller/arm-gic.h>
115 msmgpio: pinctrl@fd510000 {
116 compatible = "qcom,msm8226-pinctrl";
117 reg = <0xfd510000 0x4000>;
121 gpio-ranges = <&msmgpio 0 0 117>;
122 interrupt-controller;
123 #interrupt-cells = <2>;
124 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
127 pins = "gpio8", "gpio9";
128 function = "blsp_uart3";
129 drive-strength = <8>;