1 Qualcomm MSM8976 TLMM block
3 This binding describes the Top Level Mode Multiplexer block found in the
4 MSM8956 and MSM8976 platforms.
9 Definition: must be "qcom,msm8976-pinctrl"
13 Value type: <prop-encoded-array>
14 Definition: the base address and size of the TLMM register space.
18 Value type: <prop-encoded-array>
19 Definition: should specify the TLMM summary IRQ.
21 - interrupt-controller:
24 Definition: identifies this node as an interrupt controller
29 Definition: must be 2. Specifying the pin number and flags, as defined
30 in <dt-bindings/interrupt-controller/irq.h>
35 Definition: identifies this node as a gpio controller
40 Definition: must be 2. Specifying the pin number and flags, as defined
41 in <dt-bindings/gpio/gpio.h>
45 Definition: see ../gpio/gpio.txt
47 - gpio-reserved-ranges:
49 Definition: see ../gpio/gpio.txt
51 Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
52 a general description of GPIO and interrupt bindings.
54 Please refer to pinctrl-bindings.txt in this directory for details of the
55 common pinctrl bindings used by client devices, including the meaning of the
56 phrase "pin configuration node".
58 The pin configuration nodes act as a container for an arbitrary number of
59 subnodes. Each of these subnodes represents some desired configuration for a
60 pin, a group, or a list of pins or groups. This configuration can include the
61 mux function to select on those pin(s)/group(s), and various pin configuration
62 parameters, such as pull-up, drive strength, etc.
65 PIN CONFIGURATION NODES:
67 The name of each subnode is not important; all subnodes should be enumerated
68 and processed purely based on their content.
70 Each subnode only affects those parameters that are explicitly listed. In
71 other words, a subnode that lists a mux function but no pin configuration
72 parameters implies no information about any pin configuration parameters.
73 Similarly, a pin subnode that describes a pullup parameter implies no
74 information about e.g. the mux function.
77 The following generic properties as defined in pinctrl-bindings.txt are valid
78 to specify in a pin configuration subnode:
82 Value type: <string-array>
83 Definition: List of gpio pins affected by the properties specified in
88 Supports mux, bias and drive-strength
90 sdc1_clk, sdc1_cmd, sdc1_data,
91 sdc2_clk, sdc2_cmd, sdc2_data,
92 sdc3_clk, sdc3_cmd, sdc3_data
93 Supports bias and drive-strength
98 Definition: Specify the alternative function to be configured for the
99 specified pins. Functions are only valid for gpio pins.
102 gpio, blsp_uart1, blsp_spi1, smb_int, blsp_i2c1, blsp_spi2,
103 blsp_uart2, blsp_i2c2, gcc_gp1_clk_b, blsp_spi3,
104 qdss_tracedata_b, blsp_i2c3, gcc_gp2_clk_b, gcc_gp3_clk_b,
105 blsp_spi4, cap_int, blsp_i2c4, blsp_spi5, blsp_uart5,
106 qdss_traceclk_a, m_voc, blsp_i2c5, qdss_tracectl_a,
107 qdss_tracedata_a, blsp_spi6, blsp_uart6, qdss_tracectl_b,
108 blsp_i2c6, qdss_traceclk_b, mdp_vsync, pri_mi2s_mclk_a,
109 sec_mi2s_mclk_a, cam_mclk, cci0_i2c, cci1_i2c, blsp1_spi,
110 blsp3_spi, gcc_gp1_clk_a, gcc_gp2_clk_a, gcc_gp3_clk_a,
111 uim_batt, sd_write, uim1_data, uim1_clk, uim1_reset,
112 uim1_present, uim2_data, uim2_clk, uim2_reset,
113 uim2_present, ts_xvdd, mipi_dsi0, us_euro, ts_resout,
114 ts_sample, sec_mi2s_mclk_b, pri_mi2s, codec_reset,
115 cdc_pdm0, us_emitter, pri_mi2s_mclk_b, pri_mi2s_mclk_c,
116 lpass_slimbus, lpass_slimbus0, lpass_slimbus1, codec_int1,
117 codec_int2, wcss_bt, sdc3, wcss_wlan2, wcss_wlan1,
118 wcss_wlan0, wcss_wlan, wcss_fm, key_volp, key_snapshot,
119 key_focus, key_home, pwr_down, dmic0_clk, hdmi_int,
120 dmic0_data, wsa_vi, wsa_en, blsp_spi8, wsa_irq, blsp_i2c8,
121 pa_indicator, modem_tsync, ssbi_wtr1, gsm1_tx, gsm0_tx,
122 sdcard_det, sec_mi2s, ss_switch,
127 Definition: The specified pins should be configured as no pull.
132 Definition: The specified pins should be configured as pull down.
137 Definition: The specified pins should be configured as pull up.
142 Definition: The specified pins are configured in output mode, driven
144 Not valid for sdc pins.
149 Definition: The specified pins are configured in output mode, driven
151 Not valid for sdc pins.
156 Definition: Selects the drive strength for the specified pins, in mA.
157 Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
161 tlmm: pinctrl@1000000 {
162 compatible = "qcom,msm8976-pinctrl";
163 reg = <0x1000000 0x300000>;
164 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
167 gpio-ranges = <&tlmm 0 0 145>;
168 interrupt-controller;
169 #interrupt-cells = <2>;
171 blsp1_uart2_active: blsp1_uart2_active {
173 pins = "gpio4", "gpio5", "gpio6", "gpio7";
174 function = "blsp_uart2";
178 pins = "gpio4", "gpio5", "gpio6", "gpio7";
179 drive-strength = <2>;