1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: "http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: GENI Serial Engine QUP Wrapper Controller
10 - Mukesh Savaliya <msavaliy@codeaurora.org>
11 - Akash Asthana <akashast@codeaurora.org>
14 Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
15 is a programmable module for supporting a wide range of serial interfaces
16 like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
17 Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
18 Wrapper controller is modeled as a node with zero or more child nodes each
19 representing a serial engine.
27 description: QUP wrapper common register address and length.
37 - description: Master AHB Clock
38 - description: Slave AHB Clock
66 description: Common properties for GENI Serial Engine based I2C, SPI and
71 description: GENI Serial Engine register address and length.
78 description: Serial engine core clock needed by the device.
99 description: GENI serial engine based SPI controller. SPI in master mode
100 supports up to 50MHz, up to four chip selects, programmable
101 data path from 4 bits to 32 bits and numerous protocol
103 $ref: /spi/spi-controller.yaml#
127 description: GENI serial engine based I2C controller.
128 $ref: /schemas/i2c/i2c-controller.yaml#
145 description: Desired I2C bus clock frequency in Hz.
156 description: GENI Serial Engine based UART Controller.
157 $ref: /schemas/serial.yaml#
163 - qcom,geni-debug-uart
169 - description: UART core irq
170 - description: Wakeup irq (RX GPIO)
176 additionalProperties: false
180 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
181 #include <dt-bindings/interrupt-controller/arm-gic.h>
184 #address-cells = <2>;
188 compatible = "qcom,geni-se-qup";
189 reg = <0 0x008c0000 0 0x6000>;
190 clock-names = "m-ahb", "s-ahb";
191 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
192 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
193 #address-cells = <2>;
198 compatible = "qcom,geni-i2c";
199 reg = <0 0xa94000 0 0x4000>;
200 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
203 pinctrl-names = "default", "sleep";
204 pinctrl-0 = <&qup_1_i2c_5_active>;
205 pinctrl-1 = <&qup_1_i2c_5_sleep>;
206 #address-cells = <1>;
210 uart0: serial@a88000 {
211 compatible = "qcom,geni-uart";
212 reg = <0 0xa88000 0 0x7000>;
213 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
216 pinctrl-names = "default", "sleep";
217 pinctrl-0 = <&qup_1_uart_3_active>;
218 pinctrl-1 = <&qup_1_uart_3_sleep>;