Documentation/devicetree/bindings/timer/renesas,ostm.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/timer/renesas,ostm.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Renesas OS Timer (OSTM)
   8
   9 maintainers:
  10   - Chris Brandt <chris.brandt@renesas.com>
  11   - Geert Uytterhoeven <geert+renesas@glider.be>
  12
  13 description:
  14   The OSTM is a multi-channel 32-bit timer/counter with fixed clock source that
  15   can operate in either interval count down timer or free-running compare match
  16   mode.
  17
  18   Channels are independent from each other.
  19
  20 properties:
  21   compatible:
  22     items:
  23       - enum:
  24           - renesas,r7s72100-ostm # RZ/A1H
  25           - renesas,r7s9210-ostm  # RZ/A2M
  26       - const: renesas,ostm       # Generic
  27
  28   reg:
  29     maxItems: 1
  30
  31   interrupts:
  32     maxItems: 1
  33
  34   clocks:
  35     maxItems: 1
  36
  37   power-domains:
  38     maxItems: 1
  39
  40 required:
  41   - compatible
  42   - reg
  43   - interrupts
  44   - clocks
  45   - power-domains
  46
  47 additionalProperties: false
  48
  49 examples:
  50   - |
  51     #include <dt-bindings/clock/r7s72100-clock.h>
  52     #include <dt-bindings/interrupt-controller/arm-gic.h>
  53     ostm0: timer@fcfec000 {
  54             compatible = "renesas,r7s72100-ostm", "renesas,ostm";
  55             reg = <0xfcfec000 0x30>;
  56             interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
  57             clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
  58             power-domains = <&cpg_clocks>;
  59     };