Merge tag 'linux-kselftest-kunit-fixes-5.11-rc3' of git://git.kernel.org/pub/scm...
[linux/fpc-iii.git] / Documentation / devicetree / bindings / usb / qcom,dwc3.yaml
blob2cf525d21e054ac760541fa7ec8b553c34c30ef7
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SuperSpeed DWC3 USB SoC controller
9 maintainers:
10   - Manu Gautam <mgautam@codeaurora.org>
12 properties:
13   compatible:
14     items:
15       - enum:
16           - qcom,msm8996-dwc3
17           - qcom,msm8998-dwc3
18           - qcom,sc7180-dwc3
19           - qcom,sdm845-dwc3
20       - const: qcom,dwc3
22   reg:
23     description: Offset and length of register set for QSCRATCH wrapper
24     maxItems: 1
26   "#address-cells":
27     enum: [ 1, 2 ]
29   "#size-cells":
30     enum: [ 1, 2 ]
32   ranges: true
34   power-domains:
35     description: specifies a phandle to PM domain provider node
36     maxItems: 1
38   clocks:
39     description:
40       A list of phandle and clock-specifier pairs for the clocks
41       listed in clock-names.
42     items:
43       - description: System Config NOC clock.
44       - description: Master/Core clock, has to be >= 125 MHz
45           for SS operation and >= 60MHz for HS operation.
46       - description: System bus AXI clock.
47       - description: Mock utmi clock needed for ITP/SOF generation
48           in host mode. Its frequency should be 19.2MHz.
49       - description: Sleep clock, used for wakeup when
50           USB3 core goes into low power mode (U3).
52   clock-names:
53     items:
54       - const: cfg_noc
55       - const: core
56       - const: iface
57       - const: mock_utmi
58       - const: sleep
60   assigned-clocks:
61     items:
62       - description: Phandle and clock specifier of MOCK_UTMI_CLK.
63       - description: Phandle and clock specifoer of MASTER_CLK.
65   assigned-clock-rates:
66     items:
67       - description: Must be 19.2MHz (19200000).
68       - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
69   resets:
70     maxItems: 1
72   interconnects:
73     maxItems: 2
75   interconnect-names:
76     items:
77       - const: usb-ddr
78       - const: apps-usb
80   interrupts:
81     items:
82       - description: The interrupt that is asserted
83           when a wakeup event is received on USB2 bus.
84       - description: The interrupt that is asserted
85           when a wakeup event is received on USB3 bus.
86       - description: Wakeup event on DM line.
87       - description: Wakeup event on DP line.
89   interrupt-names:
90     items:
91       - const: hs_phy_irq
92       - const: ss_phy_irq
93       - const: dm_hs_phy_irq
94       - const: dp_hs_phy_irq
96   qcom,select-utmi-as-pipe-clk:
97     description:
98       If present, disable USB3 pipe_clk requirement.
99       Used when dwc3 operates without SSPHY and only
100       HS/FS/LS modes are supported.
101     type: boolean
103 # Required child node:
105 patternProperties:
106   "^dwc3@[0-9a-f]+$":
107     type: object
108     description:
109       A child node must exist to represent the core DWC3 IP block
110       The content of the node is defined in dwc3.txt.
112 required:
113   - compatible
114   - reg
115   - "#address-cells"
116   - "#size-cells"
117   - ranges
118   - power-domains
119   - clocks
120   - clock-names
121   - interrupts
122   - interrupt-names
124 additionalProperties: false
126 examples:
127   - |
128     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
129     #include <dt-bindings/interrupt-controller/arm-gic.h>
130     #include <dt-bindings/interrupt-controller/irq.h>
131     soc {
132         #address-cells = <2>;
133         #size-cells = <2>;
135         usb@a6f8800 {
136             compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
137             reg = <0 0x0a6f8800 0 0x400>;
139             #address-cells = <2>;
140             #size-cells = <2>;
141             ranges;
142             clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
143                      <&gcc GCC_USB30_PRIM_MASTER_CLK>,
144                      <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
145                      <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
146                      <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
147             clock-names = "cfg_noc", "core", "iface", "mock_utmi",
148                       "sleep";
150             assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
151                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
152             assigned-clock-rates = <19200000>, <150000000>;
154             interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
155                          <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
156                          <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
157                          <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
158             interrupt-names = "hs_phy_irq", "ss_phy_irq",
159                           "dm_hs_phy_irq", "dp_hs_phy_irq";
161             power-domains = <&gcc USB30_PRIM_GDSC>;
163             resets = <&gcc GCC_USB30_PRIM_BCR>;
165             dwc3@a600000 {
166                 compatible = "snps,dwc3";
167                 reg = <0 0x0a600000 0 0xcd00>;
168                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
169                 iommus = <&apps_smmu 0x740 0>;
170                 snps,dis_u2_susphy_quirk;
171                 snps,dis_enblslpm_quirk;
172                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
173                 phy-names = "usb2-phy", "usb3-phy";
174             };
175         };
176     };