2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
8 * SMP support for BMIPS
11 #include <linux/init.h>
12 #include <linux/sched.h>
13 #include <linux/sched/hotplug.h>
14 #include <linux/sched/task_stack.h>
16 #include <linux/delay.h>
17 #include <linux/smp.h>
18 #include <linux/interrupt.h>
19 #include <linux/spinlock.h>
20 #include <linux/cpu.h>
21 #include <linux/cpumask.h>
22 #include <linux/reboot.h>
24 #include <linux/compiler.h>
25 #include <linux/linkage.h>
26 #include <linux/bug.h>
27 #include <linux/kernel.h>
28 #include <linux/kexec.h>
31 #include <asm/processor.h>
32 #include <asm/bootinfo.h>
33 #include <asm/cacheflush.h>
34 #include <asm/tlbflush.h>
35 #include <asm/mipsregs.h>
36 #include <asm/bmips.h>
37 #include <asm/traps.h>
38 #include <asm/barrier.h>
39 #include <asm/cpu-features.h>
41 static int __maybe_unused max_cpus
= 1;
43 /* these may be configured by the platform code */
44 int bmips_smp_enabled
= 1;
46 cpumask_t bmips_booted_mask
;
47 unsigned long bmips_tp1_irqs
= IE_IRQ1
;
49 #define RESET_FROM_KSEG0 0x80080800
50 #define RESET_FROM_KSEG1 0xa0080800
52 static void bmips_set_reset_vec(int cpu
, u32 val
);
56 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
57 unsigned long bmips_smp_boot_sp
;
58 unsigned long bmips_smp_boot_gp
;
60 static void bmips43xx_send_ipi_single(int cpu
, unsigned int action
);
61 static void bmips5000_send_ipi_single(int cpu
, unsigned int action
);
62 static irqreturn_t
bmips43xx_ipi_interrupt(int irq
, void *dev_id
);
63 static irqreturn_t
bmips5000_ipi_interrupt(int irq
, void *dev_id
);
65 /* SW interrupts 0,1 are used for interprocessor signaling */
66 #define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0)
67 #define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1)
69 #define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift))
70 #define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
71 #define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
72 #define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0))
74 static void __init
bmips_smp_setup(void)
76 int i
, cpu
= 1, boot_cpu
= 0;
79 switch (current_cpu_type()) {
82 /* arbitration priority */
83 clear_c0_brcm_cmt_ctrl(0x30);
85 /* NBK and weak order flags */
86 set_c0_brcm_config_0(0x30000);
88 /* Find out if we are running on TP0 or TP1 */
89 boot_cpu
= !!(read_c0_brcm_cmt_local() & (1 << 31));
92 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other
94 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
95 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
102 change_c0_brcm_cmt_intr(0xf8018000,
103 (cpu_hw_intr
<< 27) | (0x03 << 15));
105 /* single core, 2 threads (2 pipelines) */
110 /* enable raceless SW interrupts */
111 set_c0_brcm_config(0x03 << 22);
113 /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
114 change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
116 /* N cores, 2 threads per core */
117 max_cpus
= (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
119 /* clear any pending SW interrupts */
120 for (i
= 0; i
< max_cpus
; i
++) {
121 write_c0_brcm_action(ACTION_CLR_IPI(i
, 0));
122 write_c0_brcm_action(ACTION_CLR_IPI(i
, 1));
130 if (!bmips_smp_enabled
)
133 /* this can be overridden by the BSP */
134 if (!board_ebase_setup
)
135 board_ebase_setup
= &bmips_ebase_setup
;
137 __cpu_number_map
[boot_cpu
] = 0;
138 __cpu_logical_map
[0] = boot_cpu
;
140 for (i
= 0; i
< max_cpus
; i
++) {
142 __cpu_number_map
[i
] = cpu
;
143 __cpu_logical_map
[cpu
] = i
;
146 set_cpu_possible(i
, 1);
147 set_cpu_present(i
, 1);
152 * IPI IRQ setup - runs on CPU0
154 static void bmips_prepare_cpus(unsigned int max_cpus
)
156 irqreturn_t (*bmips_ipi_interrupt
)(int irq
, void *dev_id
);
158 switch (current_cpu_type()) {
161 bmips_ipi_interrupt
= bmips43xx_ipi_interrupt
;
164 bmips_ipi_interrupt
= bmips5000_ipi_interrupt
;
170 if (request_irq(IPI0_IRQ
, bmips_ipi_interrupt
,
171 IRQF_PERCPU
| IRQF_NO_SUSPEND
, "smp_ipi0", NULL
))
172 panic("Can't request IPI0 interrupt");
173 if (request_irq(IPI1_IRQ
, bmips_ipi_interrupt
,
174 IRQF_PERCPU
| IRQF_NO_SUSPEND
, "smp_ipi1", NULL
))
175 panic("Can't request IPI1 interrupt");
179 * Tell the hardware to boot CPUx - runs on CPU0
181 static int bmips_boot_secondary(int cpu
, struct task_struct
*idle
)
183 bmips_smp_boot_sp
= __KSTK_TOS(idle
);
184 bmips_smp_boot_gp
= (unsigned long)task_thread_info(idle
);
188 * Initial boot sequence for secondary CPU:
189 * bmips_reset_nmi_vec @ a000_0000 ->
191 * plat_wired_tlb_setup (cached function call; optional) ->
192 * start_secondary (cached jump)
194 * Warm restart sequence:
195 * play_dead WAIT loop ->
196 * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->
197 * eret to play_dead ->
198 * bmips_secondary_reentry ->
202 pr_info("SMP: Booting CPU%d...\n", cpu
);
204 if (cpumask_test_cpu(cpu
, &bmips_booted_mask
)) {
205 /* kseg1 might not exist if this CPU enabled XKS01 */
206 bmips_set_reset_vec(cpu
, RESET_FROM_KSEG0
);
208 switch (current_cpu_type()) {
211 bmips43xx_send_ipi_single(cpu
, 0);
214 bmips5000_send_ipi_single(cpu
, 0);
218 bmips_set_reset_vec(cpu
, RESET_FROM_KSEG1
);
220 switch (current_cpu_type()) {
223 /* Reset slave TP1 if booting from TP0 */
224 if (cpu_logical_map(cpu
) == 1)
225 set_c0_brcm_cmt_ctrl(0x01);
228 write_c0_brcm_action(ACTION_BOOT_THREAD(cpu
));
231 cpumask_set_cpu(cpu
, &bmips_booted_mask
);
238 * Early setup - runs on secondary CPU after cache probe
240 static void bmips_init_secondary(void)
244 switch (current_cpu_type()) {
247 clear_c0_cause(smp_processor_id() ? C_SW1
: C_SW0
);
250 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
251 cpu_set_core(¤t_cpu_data
, (read_c0_brcm_config() >> 25) & 3);
257 * Late setup - runs on secondary CPU before entering the idle loop
259 static void bmips_smp_finish(void)
261 pr_info("SMP: CPU%d is running\n", smp_processor_id());
263 /* make sure there won't be a timer interrupt for a little while */
264 write_c0_compare(read_c0_count() + mips_hpt_frequency
/ HZ
);
267 set_c0_status(IE_SW0
| IE_SW1
| bmips_tp1_irqs
| IE_IRQ5
| ST0_IE
);
272 * BMIPS5000 raceless IPIs
274 * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
275 * IPI0 is used for SMP_RESCHEDULE_YOURSELF
276 * IPI1 is used for SMP_CALL_FUNCTION
279 static void bmips5000_send_ipi_single(int cpu
, unsigned int action
)
281 write_c0_brcm_action(ACTION_SET_IPI(cpu
, action
== SMP_CALL_FUNCTION
));
284 static irqreturn_t
bmips5000_ipi_interrupt(int irq
, void *dev_id
)
286 int action
= irq
- IPI0_IRQ
;
288 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action
));
293 generic_smp_call_function_interrupt();
298 static void bmips5000_send_ipi_mask(const struct cpumask
*mask
,
303 for_each_cpu(i
, mask
)
304 bmips5000_send_ipi_single(i
, action
);
308 * BMIPS43xx racey IPIs
310 * We use one inbound SW IRQ for each CPU.
312 * A spinlock must be held in order to keep CPUx from accidentally clearing
313 * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The
314 * same spinlock is used to protect the action masks.
317 static DEFINE_SPINLOCK(ipi_lock
);
318 static DEFINE_PER_CPU(int, ipi_action_mask
);
320 static void bmips43xx_send_ipi_single(int cpu
, unsigned int action
)
324 spin_lock_irqsave(&ipi_lock
, flags
);
325 set_c0_cause(cpu
? C_SW1
: C_SW0
);
326 per_cpu(ipi_action_mask
, cpu
) |= action
;
328 spin_unlock_irqrestore(&ipi_lock
, flags
);
331 static irqreturn_t
bmips43xx_ipi_interrupt(int irq
, void *dev_id
)
334 int action
, cpu
= irq
- IPI0_IRQ
;
336 spin_lock_irqsave(&ipi_lock
, flags
);
337 action
= __this_cpu_read(ipi_action_mask
);
338 per_cpu(ipi_action_mask
, cpu
) = 0;
339 clear_c0_cause(cpu
? C_SW1
: C_SW0
);
340 spin_unlock_irqrestore(&ipi_lock
, flags
);
342 if (action
& SMP_RESCHEDULE_YOURSELF
)
344 if (action
& SMP_CALL_FUNCTION
)
345 generic_smp_call_function_interrupt();
350 static void bmips43xx_send_ipi_mask(const struct cpumask
*mask
,
355 for_each_cpu(i
, mask
)
356 bmips43xx_send_ipi_single(i
, action
);
359 #ifdef CONFIG_HOTPLUG_CPU
361 static int bmips_cpu_disable(void)
363 unsigned int cpu
= smp_processor_id();
365 pr_info("SMP: CPU%d is offline\n", cpu
);
367 set_cpu_online(cpu
, false);
368 calculate_cpu_foreign_map();
370 clear_c0_status(IE_IRQ5
);
372 local_flush_tlb_all();
373 local_flush_icache_range(0, ~0);
378 static void bmips_cpu_die(unsigned int cpu
)
382 void __ref
play_dead(void)
386 /* flush data cache */
387 _dma_cache_wback_inv(0, ~0);
390 * Wakeup is on SW0 or SW1; disable everything else
391 * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux
392 * IRQ handlers; this clears ST0_IE and returns immediately.
394 clear_c0_cause(CAUSEF_IV
| C_SW0
| C_SW1
);
396 IE_IRQ5
| bmips_tp1_irqs
| IE_SW0
| IE_SW1
| ST0_IE
| ST0_BEV
,
397 IE_SW0
| IE_SW1
| ST0_IE
| ST0_BEV
);
398 irq_disable_hazard();
401 * wait for SW interrupt from bmips_boot_secondary(), then jump
402 * back to start_secondary()
404 __asm__
__volatile__(
406 " j bmips_secondary_reentry\n"
410 #endif /* CONFIG_HOTPLUG_CPU */
412 const struct plat_smp_ops bmips43xx_smp_ops
= {
413 .smp_setup
= bmips_smp_setup
,
414 .prepare_cpus
= bmips_prepare_cpus
,
415 .boot_secondary
= bmips_boot_secondary
,
416 .smp_finish
= bmips_smp_finish
,
417 .init_secondary
= bmips_init_secondary
,
418 .send_ipi_single
= bmips43xx_send_ipi_single
,
419 .send_ipi_mask
= bmips43xx_send_ipi_mask
,
420 #ifdef CONFIG_HOTPLUG_CPU
421 .cpu_disable
= bmips_cpu_disable
,
422 .cpu_die
= bmips_cpu_die
,
425 .kexec_nonboot_cpu
= kexec_nonboot_cpu_jump
,
429 const struct plat_smp_ops bmips5000_smp_ops
= {
430 .smp_setup
= bmips_smp_setup
,
431 .prepare_cpus
= bmips_prepare_cpus
,
432 .boot_secondary
= bmips_boot_secondary
,
433 .smp_finish
= bmips_smp_finish
,
434 .init_secondary
= bmips_init_secondary
,
435 .send_ipi_single
= bmips5000_send_ipi_single
,
436 .send_ipi_mask
= bmips5000_send_ipi_mask
,
437 #ifdef CONFIG_HOTPLUG_CPU
438 .cpu_disable
= bmips_cpu_disable
,
439 .cpu_die
= bmips_cpu_die
,
442 .kexec_nonboot_cpu
= kexec_nonboot_cpu_jump
,
446 #endif /* CONFIG_SMP */
448 /***********************************************************************
449 * BMIPS vector relocation
450 * This is primarily used for SMP boot, but it is applicable to some
451 * UP BMIPS systems as well.
452 ***********************************************************************/
454 static void bmips_wr_vec(unsigned long dst
, char *start
, char *end
)
456 memcpy((void *)dst
, start
, end
- start
);
457 dma_cache_wback(dst
, end
- start
);
458 local_flush_icache_range(dst
, dst
+ (end
- start
));
459 instruction_hazard();
462 static inline void bmips_nmi_handler_setup(void)
464 bmips_wr_vec(BMIPS_NMI_RESET_VEC
, bmips_reset_nmi_vec
,
465 bmips_reset_nmi_vec_end
);
466 bmips_wr_vec(BMIPS_WARM_RESTART_VEC
, bmips_smp_int_vec
,
467 bmips_smp_int_vec_end
);
470 struct reset_vec_info
{
475 static void bmips_set_reset_vec_remote(void *vinfo
)
477 struct reset_vec_info
*info
= vinfo
;
478 int shift
= info
->cpu
& 0x01 ? 16 : 0;
479 u32 mask
= ~(0xffff << shift
), val
= info
->val
>> 16;
482 if (smp_processor_id() > 0) {
483 smp_call_function_single(0, &bmips_set_reset_vec_remote
,
486 if (info
->cpu
& 0x02) {
487 /* BMIPS5200 "should" use mask/shift, but it's buggy */
488 bmips_write_zscm_reg(0xa0, (val
<< 16) | val
);
489 bmips_read_zscm_reg(0xa0);
491 write_c0_brcm_bootvec((read_c0_brcm_bootvec() & mask
) |
498 static void bmips_set_reset_vec(int cpu
, u32 val
)
500 struct reset_vec_info info
;
502 if (current_cpu_type() == CPU_BMIPS5000
) {
503 /* this needs to run from CPU0 (which is always online) */
506 bmips_set_reset_vec_remote(&info
);
508 void __iomem
*cbr
= BMIPS_GET_CBR();
511 __raw_writel(val
, cbr
+ BMIPS_RELO_VECTOR_CONTROL_0
);
513 if (current_cpu_type() != CPU_BMIPS4380
)
515 __raw_writel(val
, cbr
+ BMIPS_RELO_VECTOR_CONTROL_1
);
519 back_to_back_c0_hazard();
522 void bmips_ebase_setup(void)
524 unsigned long new_ebase
= ebase
;
526 BUG_ON(ebase
!= CKSEG0
);
528 switch (current_cpu_type()) {
531 * BMIPS4350 cannot relocate the normal vectors, but it
532 * can relocate the BEV=1 vectors. So CPU1 starts up at
533 * the relocated BEV=1, IV=0 general exception vector @
536 * set_uncached_handler() is used here because:
537 * - CPU1 will run this from uncached space
538 * - None of the cacheflush functions are set up yet
540 set_uncached_handler(BMIPS_WARM_RESTART_VEC
- CKSEG0
,
541 &bmips_smp_int_vec
, 0x80);
547 * 0x8000_0000: reset/NMI (initially in kseg1)
548 * 0x8000_0400: normal vectors
550 new_ebase
= 0x80000400;
551 bmips_set_reset_vec(0, RESET_FROM_KSEG0
);
555 * 0x8000_0000: reset/NMI (initially in kseg1)
556 * 0x8000_1000: normal vectors
558 new_ebase
= 0x80001000;
559 bmips_set_reset_vec(0, RESET_FROM_KSEG0
);
560 write_c0_ebase(new_ebase
);
566 board_nmi_handler_setup
= &bmips_nmi_handler_setup
;
570 asmlinkage
void __weak
plat_wired_tlb_setup(void)
573 * Called when starting/restarting a secondary CPU.
574 * Kernel stacks and other important data might only be accessible
575 * once the wired entries are present.
579 void bmips_cpu_setup(void)
581 void __iomem __maybe_unused
*cbr
= BMIPS_GET_CBR();
582 u32 __maybe_unused cfg
;
584 switch (current_cpu_type()) {
586 /* Set BIU to async mode */
587 set_c0_brcm_bus_pll(BIT(22));
590 /* put the BIU back in sync mode */
591 clear_c0_brcm_bus_pll(BIT(22));
593 /* clear BHTD to enable branch history table */
594 clear_c0_brcm_reset(BIT(16));
596 /* Flush and enable RAC */
597 cfg
= __raw_readl(cbr
+ BMIPS_RAC_CONFIG
);
598 __raw_writel(cfg
| 0x100, cbr
+ BMIPS_RAC_CONFIG
);
599 __raw_readl(cbr
+ BMIPS_RAC_CONFIG
);
601 cfg
= __raw_readl(cbr
+ BMIPS_RAC_CONFIG
);
602 __raw_writel(cfg
| 0xf, cbr
+ BMIPS_RAC_CONFIG
);
603 __raw_readl(cbr
+ BMIPS_RAC_CONFIG
);
605 cfg
= __raw_readl(cbr
+ BMIPS_RAC_ADDRESS_RANGE
);
606 __raw_writel(cfg
| 0x0fff0000, cbr
+ BMIPS_RAC_ADDRESS_RANGE
);
607 __raw_readl(cbr
+ BMIPS_RAC_ADDRESS_RANGE
);
611 /* CBG workaround for early BMIPS4380 CPUs */
612 switch (read_c0_prid()) {
617 cfg
= __raw_readl(cbr
+ BMIPS_L2_CONFIG
);
618 __raw_writel(cfg
& ~0x07000000, cbr
+ BMIPS_L2_CONFIG
);
619 __raw_readl(cbr
+ BMIPS_L2_CONFIG
);
622 /* clear BHTD to enable branch history table */
623 clear_c0_brcm_config_0(BIT(21));
626 set_c0_brcm_config_0(BIT(23));
627 set_c0_brcm_cmt_ctrl(BIT(15));
631 /* enable RDHWR, BRDHWR */
632 set_c0_brcm_config(BIT(17) | BIT(21));
635 __asm__
__volatile__(
637 " li $8, 0x5a455048\n"
638 " .word 0x4088b00f\n" /* mtc0 t0, $22, 15 */
639 " .word 0x4008b008\n" /* mfc0 t0, $22, 8 */
640 " li $9, 0x00008000\n"
642 " .word 0x4088b008\n" /* mtc0 t0, $22, 8 */
645 " .word 0x4088b00f\n" /* mtc0 t0, $22, 15 */
650 set_c0_brcm_config(BIT(27));
652 /* enable MIPS32R2 ROR instruction for XI TLB handlers */
653 __asm__
__volatile__(
654 " li $8, 0x5a455048\n"
655 " .word 0x4088b00f\n" /* mtc0 $8, $22, 15 */
657 " .word 0x4008b008\n" /* mfc0 $8, $22, 8 */
660 " .word 0x4088b008\n" /* mtc0 $8, $22, 8 */