arch/mips/kernel/smp-cps.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2013 Imagination Technologies
   4  * Author: Paul Burton <paul.burton@mips.com>
   5  */
   6
   7 #include <linux/cpu.h>
   8 #include <linux/delay.h>
   9 #include <linux/io.h>
  10 #include <linux/sched/task_stack.h>
  11 #include <linux/sched/hotplug.h>
  12 #include <linux/slab.h>
  13 #include <linux/smp.h>
  14 #include <linux/types.h>
  15 #include <linux/irq.h>
  16
  17 #include <asm/bcache.h>
  18 #include <asm/mips-cps.h>
  19 #include <asm/mips_mt.h>
  20 #include <asm/mipsregs.h>
  21 #include <asm/pm-cps.h>
  22 #include <asm/r4kcache.h>
  23 #include <asm/smp-cps.h>
  24 #include <asm/time.h>
  25 #include <asm/uasm.h>
  26
  27 static bool threads_disabled;
  28 static DECLARE_BITMAP(core_power, NR_CPUS);
  29
  30 struct core_boot_config *mips_cps_core_bootcfg;
  31
  32 static int __init setup_nothreads(char *s)
  33 {
  34         threads_disabled = true;
  35         return 0;
  36 }
  37 early_param("nothreads", setup_nothreads);
  38
  39 static unsigned core_vpe_count(unsigned int cluster, unsigned core)
  40 {
  41         if (threads_disabled)
  42                 return 1;
  43
  44         return mips_cps_numvps(cluster, core);
  45 }
  46
  47 static void __init cps_smp_setup(void)
  48 {
  49         unsigned int nclusters, ncores, nvpes, core_vpes;
  50         unsigned long core_entry;
  51         int cl, c, v;
  52
  53         /* Detect & record VPE topology */
  54         nvpes = 0;
  55         nclusters = mips_cps_numclusters();
  56         pr_info("%s topology ", cpu_has_mips_r6 ? "VP" : "VPE");
  57         for (cl = 0; cl < nclusters; cl++) {
  58                 if (cl > 0)
  59                         pr_cont(",");
  60                 pr_cont("{");
  61
  62                 ncores = mips_cps_numcores(cl);
  63                 for (c = 0; c < ncores; c++) {
  64                         core_vpes = core_vpe_count(cl, c);
  65
  66                         if (c > 0)
  67                                 pr_cont(",");
  68                         pr_cont("%u", core_vpes);
  69
  70                         /* Use the number of VPEs in cluster 0 core 0 for smp_num_siblings */
  71                         if (!cl && !c)
  72                                 smp_num_siblings = core_vpes;
  73
  74                         for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
  75                                 cpu_set_cluster(&cpu_data[nvpes + v], cl);
  76                                 cpu_set_core(&cpu_data[nvpes + v], c);
  77                                 cpu_set_vpe_id(&cpu_data[nvpes + v], v);
  78                         }
  79
  80                         nvpes += core_vpes;
  81                 }
  82
  83                 pr_cont("}");
  84         }
  85         pr_cont(" total %u\n", nvpes);
  86
  87         /* Indicate present CPUs (CPU being synonymous with VPE) */
  88         for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
  89                 set_cpu_possible(v, cpu_cluster(&cpu_data[v]) == 0);
  90                 set_cpu_present(v, cpu_cluster(&cpu_data[v]) == 0);
  91                 __cpu_number_map[v] = v;
  92                 __cpu_logical_map[v] = v;
  93         }
  94
  95         /* Set a coherent default CCA (CWB) */
  96         change_c0_config(CONF_CM_CMASK, 0x5);
  97
  98         /* Core 0 is powered up (we're running on it) */
  99         bitmap_set(core_power, 0, 1);
 100
 101         /* Initialise core 0 */
 102         mips_cps_core_init();
 103
 104         /* Make core 0 coherent with everything */
 105         write_gcr_cl_coherence(0xff);
 106
 107         if (mips_cm_revision() >= CM_REV_CM3) {
 108                 core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
 109                 write_gcr_bev_base(core_entry);
 110         }
 111
 112 #ifdef CONFIG_MIPS_MT_FPAFF
 113         /* If we have an FPU, enroll ourselves in the FPU-full mask */
 114         if (cpu_has_fpu)
 115                 cpumask_set_cpu(0, &mt_fpu_cpumask);
 116 #endif /* CONFIG_MIPS_MT_FPAFF */
 117 }
 118
 119 static void __init cps_prepare_cpus(unsigned int max_cpus)
 120 {
 121         unsigned ncores, core_vpes, c, cca;
 122         bool cca_unsuitable, cores_limited;
 123         u32 *entry_code;
 124
 125         mips_mt_set_cpuoptions();
 126
 127         /* Detect whether the CCA is unsuited to multi-core SMP */
 128         cca = read_c0_config() & CONF_CM_CMASK;
 129         switch (cca) {
 130         case 0x4: /* CWBE */
 131         case 0x5: /* CWB */
 132                 /* The CCA is coherent, multi-core is fine */
 133                 cca_unsuitable = false;
 134                 break;
 135
 136         default:
 137                 /* CCA is not coherent, multi-core is not usable */
 138                 cca_unsuitable = true;
 139         }
 140
 141         /* Warn the user if the CCA prevents multi-core */
 142         cores_limited = false;
 143         if (cca_unsuitable || cpu_has_dc_aliases) {
 144                 for_each_present_cpu(c) {
 145                         if (cpus_are_siblings(smp_processor_id(), c))
 146                                 continue;
 147
 148                         set_cpu_present(c, false);
 149                         cores_limited = true;
 150                 }
 151         }
 152         if (cores_limited)
 153                 pr_warn("Using only one core due to %s%s%s\n",
 154                         cca_unsuitable ? "unsuitable CCA" : "",
 155                         (cca_unsuitable && cpu_has_dc_aliases) ? " & " : "",
 156                         cpu_has_dc_aliases ? "dcache aliasing" : "");
 157
 158         /*
 159          * Patch the start of mips_cps_core_entry to provide:
 160          *
 161          * s0 = kseg0 CCA
 162          */
 163         entry_code = (u32 *)&mips_cps_core_entry;
 164         uasm_i_addiu(&entry_code, 16, 0, cca);
 165         blast_dcache_range((unsigned long)&mips_cps_core_entry,
 166                            (unsigned long)entry_code);
 167         bc_wback_inv((unsigned long)&mips_cps_core_entry,
 168                      (void *)entry_code - (void *)&mips_cps_core_entry);
 169         __sync();
 170
 171         /* Allocate core boot configuration structs */
 172         ncores = mips_cps_numcores(0);
 173         mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg),
 174                                         GFP_KERNEL);
 175         if (!mips_cps_core_bootcfg) {
 176                 pr_err("Failed to allocate boot config for %u cores\n", ncores);
 177                 goto err_out;
 178         }
 179
 180         /* Allocate VPE boot configuration structs */
 181         for (c = 0; c < ncores; c++) {
 182                 core_vpes = core_vpe_count(0, c);
 183                 mips_cps_core_bootcfg[c].vpe_config = kcalloc(core_vpes,
 184                                 sizeof(*mips_cps_core_bootcfg[c].vpe_config),
 185                                 GFP_KERNEL);
 186                 if (!mips_cps_core_bootcfg[c].vpe_config) {
 187                         pr_err("Failed to allocate %u VPE boot configs\n",
 188                                core_vpes);
 189                         goto err_out;
 190                 }
 191         }
 192
 193         /* Mark this CPU as booted */
 194         atomic_set(&mips_cps_core_bootcfg[cpu_core(&current_cpu_data)].vpe_mask,
 195                    1 << cpu_vpe_id(&current_cpu_data));
 196
 197         return;
 198 err_out:
 199         /* Clean up allocations */
 200         if (mips_cps_core_bootcfg) {
 201                 for (c = 0; c < ncores; c++)
 202                         kfree(mips_cps_core_bootcfg[c].vpe_config);
 203                 kfree(mips_cps_core_bootcfg);
 204                 mips_cps_core_bootcfg = NULL;
 205         }
 206
 207         /* Effectively disable SMP by declaring CPUs not present */
 208         for_each_possible_cpu(c) {
 209                 if (c == 0)
 210                         continue;
 211                 set_cpu_present(c, false);
 212         }
 213 }
 214
 215 static void boot_core(unsigned int core, unsigned int vpe_id)
 216 {
 217         u32 stat, seq_state;
 218         unsigned timeout;
 219
 220         /* Select the appropriate core */
 221         mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
 222
 223         /* Set its reset vector */
 224         write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
 225
 226         /* Ensure its coherency is disabled */
 227         write_gcr_co_coherence(0);
 228
 229         /* Start it with the legacy memory map and exception base */
 230         write_gcr_co_reset_ext_base(CM_GCR_Cx_RESET_EXT_BASE_UEB);
 231
 232         /* Ensure the core can access the GCRs */
 233         set_gcr_access(1 << core);
 234
 235         if (mips_cpc_present()) {
 236                 /* Reset the core */
 237                 mips_cpc_lock_other(core);
 238
 239                 if (mips_cm_revision() >= CM_REV_CM3) {
 240                         /* Run only the requested VP following the reset */
 241                         write_cpc_co_vp_stop(0xf);
 242                         write_cpc_co_vp_run(1 << vpe_id);
 243
 244                         /*
 245                          * Ensure that the VP_RUN register is written before the
 246                          * core leaves reset.
 247                          */
 248                         wmb();
 249                 }
 250
 251                 write_cpc_co_cmd(CPC_Cx_CMD_RESET);
 252
 253                 timeout = 100;
 254                 while (true) {
 255                         stat = read_cpc_co_stat_conf();
 256                         seq_state = stat & CPC_Cx_STAT_CONF_SEQSTATE;
 257                         seq_state >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
 258
 259                         /* U6 == coherent execution, ie. the core is up */
 260                         if (seq_state == CPC_Cx_STAT_CONF_SEQSTATE_U6)
 261                                 break;
 262
 263                         /* Delay a little while before we start warning */
 264                         if (timeout) {
 265                                 timeout--;
 266                                 mdelay(10);
 267                                 continue;
 268                         }
 269
 270                         pr_warn("Waiting for core %u to start... STAT_CONF=0x%x\n",
 271                                 core, stat);
 272                         mdelay(1000);
 273                 }
 274
 275                 mips_cpc_unlock_other();
 276         } else {
 277                 /* Take the core out of reset */
 278                 write_gcr_co_reset_release(0);
 279         }
 280
 281         mips_cm_unlock_other();
 282
 283         /* The core is now powered up */
 284         bitmap_set(core_power, core, 1);
 285 }
 286
 287 static void remote_vpe_boot(void *dummy)
 288 {
 289         unsigned core = cpu_core(&current_cpu_data);
 290         struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
 291
 292         mips_cps_boot_vpes(core_cfg, cpu_vpe_id(&current_cpu_data));
 293 }
 294
 295 static int cps_boot_secondary(int cpu, struct task_struct *idle)
 296 {
 297         unsigned core = cpu_core(&cpu_data[cpu]);
 298         unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
 299         struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
 300         struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
 301         unsigned long core_entry;
 302         unsigned int remote;
 303         int err;
 304
 305         /* We don't yet support booting CPUs in other clusters */
 306         if (cpu_cluster(&cpu_data[cpu]) != cpu_cluster(&raw_current_cpu_data))
 307                 return -ENOSYS;
 308
 309         vpe_cfg->pc = (unsigned long)&smp_bootstrap;
 310         vpe_cfg->sp = __KSTK_TOS(idle);
 311         vpe_cfg->gp = (unsigned long)task_thread_info(idle);
 312
 313         atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);
 314
 315         preempt_disable();
 316
 317         if (!test_bit(core, core_power)) {
 318                 /* Boot a VPE on a powered down core */
 319                 boot_core(core, vpe_id);
 320                 goto out;
 321         }
 322
 323         if (cpu_has_vp) {
 324                 mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
 325                 core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry);
 326                 write_gcr_co_reset_base(core_entry);
 327                 mips_cm_unlock_other();
 328         }
 329
 330         if (!cpus_are_siblings(cpu, smp_processor_id())) {
 331                 /* Boot a VPE on another powered up core */
 332                 for (remote = 0; remote < NR_CPUS; remote++) {
 333                         if (!cpus_are_siblings(cpu, remote))
 334                                 continue;
 335                         if (cpu_online(remote))
 336                                 break;
 337                 }
 338                 if (remote >= NR_CPUS) {
 339                         pr_crit("No online CPU in core %u to start CPU%d\n",
 340                                 core, cpu);
 341                         goto out;
 342                 }
 343
 344                 err = smp_call_function_single(remote, remote_vpe_boot,
 345                                                NULL, 1);
 346                 if (err)
 347                         panic("Failed to call remote CPU\n");
 348                 goto out;
 349         }
 350
 351         BUG_ON(!cpu_has_mipsmt && !cpu_has_vp);
 352
 353         /* Boot a VPE on this core */
 354         mips_cps_boot_vpes(core_cfg, vpe_id);
 355 out:
 356         preempt_enable();
 357         return 0;
 358 }
 359
 360 static void cps_init_secondary(void)
 361 {
 362         /* Disable MT - we only want to run 1 TC per VPE */
 363         if (cpu_has_mipsmt)
 364                 dmt();
 365
 366         if (mips_cm_revision() >= CM_REV_CM3) {
 367                 unsigned int ident = read_gic_vl_ident();
 368
 369                 /*
 370                  * Ensure that our calculation of the VP ID matches up with
 371                  * what the GIC reports, otherwise we'll have configured
 372                  * interrupts incorrectly.
 373                  */
 374                 BUG_ON(ident != mips_cm_vp_id(smp_processor_id()));
 375         }
 376
 377         if (cpu_has_veic)
 378                 clear_c0_status(ST0_IM);
 379         else
 380                 change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
 381                                          STATUSF_IP4 | STATUSF_IP5 |
 382                                          STATUSF_IP6 | STATUSF_IP7);
 383 }
 384
 385 static void cps_smp_finish(void)
 386 {
 387         write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
 388
 389 #ifdef CONFIG_MIPS_MT_FPAFF
 390         /* If we have an FPU, enroll ourselves in the FPU-full mask */
 391         if (cpu_has_fpu)
 392                 cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
 393 #endif /* CONFIG_MIPS_MT_FPAFF */
 394
 395         local_irq_enable();
 396 }
 397
 398 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_KEXEC)
 399
 400 enum cpu_death {
 401         CPU_DEATH_HALT,
 402         CPU_DEATH_POWER,
 403 };
 404
 405 static void cps_shutdown_this_cpu(enum cpu_death death)
 406 {
 407         unsigned int cpu, core, vpe_id;
 408
 409         cpu = smp_processor_id();
 410         core = cpu_core(&cpu_data[cpu]);
 411
 412         if (death == CPU_DEATH_HALT) {
 413                 vpe_id = cpu_vpe_id(&cpu_data[cpu]);
 414
 415                 pr_debug("Halting core %d VP%d\n", core, vpe_id);
 416                 if (cpu_has_mipsmt) {
 417                         /* Halt this TC */
 418                         write_c0_tchalt(TCHALT_H);
 419                         instruction_hazard();
 420                 } else if (cpu_has_vp) {
 421                         write_cpc_cl_vp_stop(1 << vpe_id);
 422
 423                         /* Ensure that the VP_STOP register is written */
 424                         wmb();
 425                 }
 426         } else {
 427                 pr_debug("Gating power to core %d\n", core);
 428                 /* Power down the core */
 429                 cps_pm_enter_state(CPS_PM_POWER_GATED);
 430         }
 431 }
 432
 433 #ifdef CONFIG_KEXEC
 434
 435 static void cps_kexec_nonboot_cpu(void)
 436 {
 437         if (cpu_has_mipsmt || cpu_has_vp)
 438                 cps_shutdown_this_cpu(CPU_DEATH_HALT);
 439         else
 440                 cps_shutdown_this_cpu(CPU_DEATH_POWER);
 441 }
 442
 443 #endif /* CONFIG_KEXEC */
 444
 445 #endif /* CONFIG_HOTPLUG_CPU || CONFIG_KEXEC */
 446
 447 #ifdef CONFIG_HOTPLUG_CPU
 448
 449 static int cps_cpu_disable(void)
 450 {
 451         unsigned cpu = smp_processor_id();
 452         struct core_boot_config *core_cfg;
 453
 454         if (!cpu)
 455                 return -EBUSY;
 456
 457         if (!cps_pm_support_state(CPS_PM_POWER_GATED))
 458                 return -EINVAL;
 459
 460         core_cfg = &mips_cps_core_bootcfg[cpu_core(&current_cpu_data)];
 461         atomic_sub(1 << cpu_vpe_id(&current_cpu_data), &core_cfg->vpe_mask);
 462         smp_mb__after_atomic();
 463         set_cpu_online(cpu, false);
 464         calculate_cpu_foreign_map();
 465         irq_migrate_all_off_this_cpu();
 466
 467         return 0;
 468 }
 469
 470 static unsigned cpu_death_sibling;
 471 static enum cpu_death cpu_death;
 472
 473 void play_dead(void)
 474 {
 475         unsigned int cpu;
 476
 477         local_irq_disable();
 478         idle_task_exit();
 479         cpu = smp_processor_id();
 480         cpu_death = CPU_DEATH_POWER;
 481
 482         pr_debug("CPU%d going offline\n", cpu);
 483
 484         if (cpu_has_mipsmt || cpu_has_vp) {
 485                 /* Look for another online VPE within the core */
 486                 for_each_online_cpu(cpu_death_sibling) {
 487                         if (!cpus_are_siblings(cpu, cpu_death_sibling))
 488                                 continue;
 489
 490                         /*
 491                          * There is an online VPE within the core. Just halt
 492                          * this TC and leave the core alone.
 493                          */
 494                         cpu_death = CPU_DEATH_HALT;
 495                         break;
 496                 }
 497         }
 498
 499         /* This CPU has chosen its way out */
 500         (void)cpu_report_death();
 501
 502         cps_shutdown_this_cpu(cpu_death);
 503
 504         /* This should never be reached */
 505         panic("Failed to offline CPU %u", cpu);
 506 }
 507
 508 static void wait_for_sibling_halt(void *ptr_cpu)
 509 {
 510         unsigned cpu = (unsigned long)ptr_cpu;
 511         unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
 512         unsigned halted;
 513         unsigned long flags;
 514
 515         do {
 516                 local_irq_save(flags);
 517                 settc(vpe_id);
 518                 halted = read_tc_c0_tchalt();
 519                 local_irq_restore(flags);
 520         } while (!(halted & TCHALT_H));
 521 }
 522
 523 static void cps_cpu_die(unsigned int cpu)
 524 {
 525         unsigned core = cpu_core(&cpu_data[cpu]);
 526         unsigned int vpe_id = cpu_vpe_id(&cpu_data[cpu]);
 527         ktime_t fail_time;
 528         unsigned stat;
 529         int err;
 530
 531         /* Wait for the cpu to choose its way out */
 532         if (!cpu_wait_death(cpu, 5)) {
 533                 pr_err("CPU%u: didn't offline\n", cpu);
 534                 return;
 535         }
 536
 537         /*
 538          * Now wait for the CPU to actually offline. Without doing this that
 539          * offlining may race with one or more of:
 540          *
 541          *   - Onlining the CPU again.
 542          *   - Powering down the core if another VPE within it is offlined.
 543          *   - A sibling VPE entering a non-coherent state.
 544          *
 545          * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing
 546          * with which we could race, so do nothing.
 547          */
 548         if (cpu_death == CPU_DEATH_POWER) {
 549                 /*
 550                  * Wait for the core to enter a powered down or clock gated
 551                  * state, the latter happening when a JTAG probe is connected
 552                  * in which case the CPC will refuse to power down the core.
 553                  */
 554                 fail_time = ktime_add_ms(ktime_get(), 2000);
 555                 do {
 556                         mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
 557                         mips_cpc_lock_other(core);
 558                         stat = read_cpc_co_stat_conf();
 559                         stat &= CPC_Cx_STAT_CONF_SEQSTATE;
 560                         stat >>= __ffs(CPC_Cx_STAT_CONF_SEQSTATE);
 561                         mips_cpc_unlock_other();
 562                         mips_cm_unlock_other();
 563
 564                         if (stat == CPC_Cx_STAT_CONF_SEQSTATE_D0 ||
 565                             stat == CPC_Cx_STAT_CONF_SEQSTATE_D2 ||
 566                             stat == CPC_Cx_STAT_CONF_SEQSTATE_U2)
 567                                 break;
 568
 569                         /*
 570                          * The core ought to have powered down, but didn't &
 571                          * now we don't really know what state it's in. It's
 572                          * likely that its _pwr_up pin has been wired to logic
 573                          * 1 & it powered back up as soon as we powered it
 574                          * down...
 575                          *
 576                          * The best we can do is warn the user & continue in
 577                          * the hope that the core is doing nothing harmful &
 578                          * might behave properly if we online it later.
 579                          */
 580                         if (WARN(ktime_after(ktime_get(), fail_time),
 581                                  "CPU%u hasn't powered down, seq. state %u\n",
 582                                  cpu, stat))
 583                                 break;
 584                 } while (1);
 585
 586                 /* Indicate the core is powered off */
 587                 bitmap_clear(core_power, core, 1);
 588         } else if (cpu_has_mipsmt) {
 589                 /*
 590                  * Have a CPU with access to the offlined CPUs registers wait
 591                  * for its TC to halt.
 592                  */
 593                 err = smp_call_function_single(cpu_death_sibling,
 594                                                wait_for_sibling_halt,
 595                                                (void *)(unsigned long)cpu, 1);
 596                 if (err)
 597                         panic("Failed to call remote sibling CPU\n");
 598         } else if (cpu_has_vp) {
 599                 do {
 600                         mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
 601                         stat = read_cpc_co_vp_running();
 602                         mips_cm_unlock_other();
 603                 } while (stat & (1 << vpe_id));
 604         }
 605 }
 606
 607 #endif /* CONFIG_HOTPLUG_CPU */
 608
 609 static const struct plat_smp_ops cps_smp_ops = {
 610         .smp_setup              = cps_smp_setup,
 611         .prepare_cpus           = cps_prepare_cpus,
 612         .boot_secondary         = cps_boot_secondary,
 613         .init_secondary         = cps_init_secondary,
 614         .smp_finish             = cps_smp_finish,
 615         .send_ipi_single        = mips_smp_send_ipi_single,
 616         .send_ipi_mask          = mips_smp_send_ipi_mask,
 617 #ifdef CONFIG_HOTPLUG_CPU
 618         .cpu_disable            = cps_cpu_disable,
 619         .cpu_die                = cps_cpu_die,
 620 #endif
 621 #ifdef CONFIG_KEXEC
 622         .kexec_nonboot_cpu      = cps_kexec_nonboot_cpu,
 623 #endif
 624 };
 625
 626 bool mips_cps_smp_in_use(void)
 627 {
 628         extern const struct plat_smp_ops *mp_ops;
 629         return mp_ops == &cps_smp_ops;
 630 }
 631
 632 int register_cps_smp_ops(void)
 633 {
 634         if (!mips_cm_present()) {
 635                 pr_warn("MIPS CPS SMP unable to proceed without a CM\n");
 636                 return -ENODEV;
 637         }
 638
 639         /* check we have a GIC - we need one for IPIs */
 640         if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX)) {
 641                 pr_warn("MIPS CPS SMP unable to proceed without a GIC\n");
 642                 return -ENODEV;
 643         }
 644
 645         register_smp_ops(&cps_smp_ops);
 646         return 0;
 647 }