arch/mips/ralink/rt305x.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *
   4  * Parts of this file are based on Ralink's 2.6.21 BSP
   5  *
   6  * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
   7  * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   8  * Copyright (C) 2013 John Crispin <john@phrozen.org>
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/bug.h>
  14
  15 #include <asm/io.h>
  16 #include <asm/mipsregs.h>
  17 #include <asm/mach-ralink/ralink_regs.h>
  18 #include <asm/mach-ralink/rt305x.h>
  19 #include <asm/mach-ralink/pinmux.h>
  20
  21 #include "common.h"
  22
  23 static struct rt2880_pmx_func i2c_func[] =  { FUNC("i2c", 0, 1, 2) };
  24 static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
  25 static struct rt2880_pmx_func uartf_func[] = {
  26         FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8),
  27         FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8),
  28         FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8),
  29         FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8),
  30         FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4),
  31         FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4),
  32         FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4),
  33 };
  34 static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
  35 static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) };
  36 static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
  37 static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) };
  38 static struct rt2880_pmx_func rt5350_cs1_func[] = {
  39         FUNC("spi_cs1", 0, 27, 1),
  40         FUNC("wdg_cs1", 1, 27, 1),
  41 };
  42 static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
  43 static struct rt2880_pmx_func rt3352_rgmii_func[] = {
  44         FUNC("rgmii", 0, 24, 12)
  45 };
  46 static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) };
  47 static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) };
  48 static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) };
  49 static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) };
  50 static struct rt2880_pmx_func rt3352_cs1_func[] = {
  51         FUNC("spi_cs1", 0, 45, 1),
  52         FUNC("wdg_cs1", 1, 45, 1),
  53 };
  54
  55 static struct rt2880_pmx_group rt3050_pinmux_data[] = {
  56         GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
  57         GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
  58         GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
  59                 RT305X_GPIO_MODE_UART0_SHIFT),
  60         GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
  61         GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
  62         GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
  63         GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
  64         GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM),
  65         { 0 }
  66 };
  67
  68 static struct rt2880_pmx_group rt3352_pinmux_data[] = {
  69         GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
  70         GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
  71         GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
  72                 RT305X_GPIO_MODE_UART0_SHIFT),
  73         GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
  74         GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
  75         GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
  76         GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
  77         GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA),
  78         GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA),
  79         GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
  80         GRP("spi_cs1", rt3352_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1),
  81         { 0 }
  82 };
  83
  84 static struct rt2880_pmx_group rt5350_pinmux_data[] = {
  85         GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
  86         GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
  87         GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
  88                 RT305X_GPIO_MODE_UART0_SHIFT),
  89         GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
  90         GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
  91         GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
  92         GRP("spi_cs1", rt5350_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1),
  93         { 0 }
  94 };
  95
  96 static unsigned long rt5350_get_mem_size(void)
  97 {
  98         void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
  99         unsigned long ret;
 100         u32 t;
 101
 102         t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG);
 103         t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) &
 104                 RT5350_SYSCFG0_DRAM_SIZE_MASK;
 105
 106         switch (t) {
 107         case RT5350_SYSCFG0_DRAM_SIZE_2M:
 108                 ret = 2;
 109                 break;
 110         case RT5350_SYSCFG0_DRAM_SIZE_8M:
 111                 ret = 8;
 112                 break;
 113         case RT5350_SYSCFG0_DRAM_SIZE_16M:
 114                 ret = 16;
 115                 break;
 116         case RT5350_SYSCFG0_DRAM_SIZE_32M:
 117                 ret = 32;
 118                 break;
 119         case RT5350_SYSCFG0_DRAM_SIZE_64M:
 120                 ret = 64;
 121                 break;
 122         default:
 123                 panic("rt5350: invalid DRAM size: %u", t);
 124                 break;
 125         }
 126
 127         return ret;
 128 }
 129
 130 void __init ralink_clk_init(void)
 131 {
 132         unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
 133         unsigned long wmac_rate = 40000000;
 134
 135         u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
 136
 137         if (soc_is_rt305x() || soc_is_rt3350()) {
 138                 t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
 139                      RT305X_SYSCFG_CPUCLK_MASK;
 140                 switch (t) {
 141                 case RT305X_SYSCFG_CPUCLK_LOW:
 142                         cpu_rate = 320000000;
 143                         break;
 144                 case RT305X_SYSCFG_CPUCLK_HIGH:
 145                         cpu_rate = 384000000;
 146                         break;
 147                 }
 148                 sys_rate = uart_rate = wdt_rate = cpu_rate / 3;
 149         } else if (soc_is_rt3352()) {
 150                 t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
 151                      RT3352_SYSCFG0_CPUCLK_MASK;
 152                 switch (t) {
 153                 case RT3352_SYSCFG0_CPUCLK_LOW:
 154                         cpu_rate = 384000000;
 155                         break;
 156                 case RT3352_SYSCFG0_CPUCLK_HIGH:
 157                         cpu_rate = 400000000;
 158                         break;
 159                 }
 160                 sys_rate = wdt_rate = cpu_rate / 3;
 161                 uart_rate = 40000000;
 162         } else if (soc_is_rt5350()) {
 163                 t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
 164                      RT5350_SYSCFG0_CPUCLK_MASK;
 165                 switch (t) {
 166                 case RT5350_SYSCFG0_CPUCLK_360:
 167                         cpu_rate = 360000000;
 168                         sys_rate = cpu_rate / 3;
 169                         break;
 170                 case RT5350_SYSCFG0_CPUCLK_320:
 171                         cpu_rate = 320000000;
 172                         sys_rate = cpu_rate / 4;
 173                         break;
 174                 case RT5350_SYSCFG0_CPUCLK_300:
 175                         cpu_rate = 300000000;
 176                         sys_rate = cpu_rate / 3;
 177                         break;
 178                 default:
 179                         BUG();
 180                 }
 181                 uart_rate = 40000000;
 182                 wdt_rate = sys_rate;
 183         } else {
 184                 BUG();
 185         }
 186
 187         if (soc_is_rt3352() || soc_is_rt5350()) {
 188                 u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
 189
 190                 if (!(val & RT3352_CLKCFG0_XTAL_SEL))
 191                         wmac_rate = 20000000;
 192         }
 193
 194         ralink_clk_add("cpu", cpu_rate);
 195         ralink_clk_add("sys", sys_rate);
 196         ralink_clk_add("10000900.i2c", uart_rate);
 197         ralink_clk_add("10000a00.i2s", uart_rate);
 198         ralink_clk_add("10000b00.spi", sys_rate);
 199         ralink_clk_add("10000b40.spi", sys_rate);
 200         ralink_clk_add("10000100.timer", wdt_rate);
 201         ralink_clk_add("10000120.watchdog", wdt_rate);
 202         ralink_clk_add("10000500.uart", uart_rate);
 203         ralink_clk_add("10000c00.uartlite", uart_rate);
 204         ralink_clk_add("10100000.ethernet", sys_rate);
 205         ralink_clk_add("10180000.wmac", wmac_rate);
 206 }
 207
 208 void __init ralink_of_remap(void)
 209 {
 210         rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");
 211         rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc");
 212
 213         if (!rt_sysc_membase || !rt_memc_membase)
 214                 panic("Failed to remap core resources");
 215 }
 216
 217 void prom_soc_init(struct ralink_soc_info *soc_info)
 218 {
 219         void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
 220         unsigned char *name;
 221         u32 n0;
 222         u32 n1;
 223         u32 id;
 224
 225         n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
 226         n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
 227
 228         if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) {
 229                 unsigned long icache_sets;
 230
 231                 icache_sets = (read_c0_config1() >> 22) & 7;
 232                 if (icache_sets == 1) {
 233                         ralink_soc = RT305X_SOC_RT3050;
 234                         name = "RT3050";
 235                         soc_info->compatible = "ralink,rt3050-soc";
 236                 } else {
 237                         ralink_soc = RT305X_SOC_RT3052;
 238                         name = "RT3052";
 239                         soc_info->compatible = "ralink,rt3052-soc";
 240                 }
 241         } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
 242                 ralink_soc = RT305X_SOC_RT3350;
 243                 name = "RT3350";
 244                 soc_info->compatible = "ralink,rt3350-soc";
 245         } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
 246                 ralink_soc = RT305X_SOC_RT3352;
 247                 name = "RT3352";
 248                 soc_info->compatible = "ralink,rt3352-soc";
 249         } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
 250                 ralink_soc = RT305X_SOC_RT5350;
 251                 name = "RT5350";
 252                 soc_info->compatible = "ralink,rt5350-soc";
 253         } else {
 254                 panic("rt305x: unknown SoC, n0:%08x n1:%08x", n0, n1);
 255         }
 256
 257         id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
 258
 259         snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
 260                 "Ralink %s id:%u rev:%u",
 261                 name,
 262                 (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
 263                 (id & CHIP_ID_REV_MASK));
 264
 265         soc_info->mem_base = RT305X_SDRAM_BASE;
 266         if (soc_is_rt5350()) {
 267                 soc_info->mem_size = rt5350_get_mem_size();
 268                 rt2880_pinmux_data = rt5350_pinmux_data;
 269         } else if (soc_is_rt305x() || soc_is_rt3350()) {
 270                 soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
 271                 soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
 272                 rt2880_pinmux_data = rt3050_pinmux_data;
 273         } else if (soc_is_rt3352()) {
 274                 soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
 275                 soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
 276                 rt2880_pinmux_data = rt3352_pinmux_data;
 277         }
 278 }