arch/powerpc/include/asm/processor.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 #ifndef _ASM_POWERPC_PROCESSOR_H
   3 #define _ASM_POWERPC_PROCESSOR_H
   4
   5 /*
   6  * Copyright (C) 2001 PPC 64 Team, IBM Corp
   7  */
   8
   9 #include <vdso/processor.h>
  10
  11 #include <asm/reg.h>
  12
  13 #ifdef CONFIG_VSX
  14 #define TS_FPRWIDTH 2
  15
  16 #ifdef __BIG_ENDIAN__
  17 #define TS_FPROFFSET 0
  18 #define TS_VSRLOWOFFSET 1
  19 #else
  20 #define TS_FPROFFSET 1
  21 #define TS_VSRLOWOFFSET 0
  22 #endif
  23
  24 #else
  25 #define TS_FPRWIDTH 1
  26 #define TS_FPROFFSET 0
  27 #endif
  28
  29 #ifdef CONFIG_PPC64
  30 /* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
  31 #define PPR_PRIORITY 3
  32 #ifdef __ASSEMBLY__
  33 #define DEFAULT_PPR (PPR_PRIORITY << 50)
  34 #else
  35 #define DEFAULT_PPR ((u64)PPR_PRIORITY << 50)
  36 #endif /* __ASSEMBLY__ */
  37 #endif /* CONFIG_PPC64 */
  38
  39 #ifndef __ASSEMBLY__
  40 #include <linux/types.h>
  41 #include <linux/thread_info.h>
  42 #include <asm/ptrace.h>
  43 #include <asm/hw_breakpoint.h>
  44
  45 /* We do _not_ want to define new machine types at all, those must die
  46  * in favor of using the device-tree
  47  * -- BenH.
  48  */
  49
  50 /* PREP sub-platform types. Unused */
  51 #define _PREP_Motorola  0x01    /* motorola prep */
  52 #define _PREP_Firm      0x02    /* firmworks prep */
  53 #define _PREP_IBM       0x00    /* ibm prep */
  54 #define _PREP_Bull      0x03    /* bull prep */
  55
  56 /* CHRP sub-platform types. These are arbitrary */
  57 #define _CHRP_Motorola  0x04    /* motorola chrp, the cobra */
  58 #define _CHRP_IBM       0x05    /* IBM chrp, the longtrail and longtrail 2 */
  59 #define _CHRP_Pegasos   0x06    /* Genesi/bplan's Pegasos and Pegasos2 */
  60 #define _CHRP_briq      0x07    /* TotalImpact's briQ */
  61
  62 #if defined(__KERNEL__) && defined(CONFIG_PPC32)
  63
  64 extern int _chrp_type;
  65
  66 #endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
  67
  68 #ifdef __KERNEL__
  69
  70 #ifdef CONFIG_PPC64
  71 #include <asm/task_size_64.h>
  72 #else
  73 #include <asm/task_size_32.h>
  74 #endif
  75
  76 struct task_struct;
  77 void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
  78 void release_thread(struct task_struct *);
  79
  80 #define TS_FPR(i) fp_state.fpr[i][TS_FPROFFSET]
  81 #define TS_CKFPR(i) ckfp_state.fpr[i][TS_FPROFFSET]
  82
  83 /* FP and VSX 0-31 register set */
  84 struct thread_fp_state {
  85         u64     fpr[32][TS_FPRWIDTH] __attribute__((aligned(16)));
  86         u64     fpscr;          /* Floating point status */
  87 };
  88
  89 /* Complete AltiVec register set including VSCR */
  90 struct thread_vr_state {
  91         vector128       vr[32] __attribute__((aligned(16)));
  92         vector128       vscr __attribute__((aligned(16)));
  93 };
  94
  95 struct debug_reg {
  96 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
  97         /*
  98          * The following help to manage the use of Debug Control Registers
  99          * om the BookE platforms.
 100          */
 101         uint32_t        dbcr0;
 102         uint32_t        dbcr1;
 103 #ifdef CONFIG_BOOKE
 104         uint32_t        dbcr2;
 105 #endif
 106         /*
 107          * The stored value of the DBSR register will be the value at the
 108          * last debug interrupt. This register can only be read from the
 109          * user (will never be written to) and has value while helping to
 110          * describe the reason for the last debug trap.  Torez
 111          */
 112         uint32_t        dbsr;
 113         /*
 114          * The following will contain addresses used by debug applications
 115          * to help trace and trap on particular address locations.
 116          * The bits in the Debug Control Registers above help define which
 117          * of the following registers will contain valid data and/or addresses.
 118          */
 119         unsigned long   iac1;
 120         unsigned long   iac2;
 121 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 122         unsigned long   iac3;
 123         unsigned long   iac4;
 124 #endif
 125         unsigned long   dac1;
 126         unsigned long   dac2;
 127 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 128         unsigned long   dvc1;
 129         unsigned long   dvc2;
 130 #endif
 131 #endif
 132 };
 133
 134 struct thread_struct {
 135         unsigned long   ksp;            /* Kernel stack pointer */
 136
 137 #ifdef CONFIG_PPC64
 138         unsigned long   ksp_vsid;
 139 #endif
 140         struct pt_regs  *regs;          /* Pointer to saved register state */
 141 #ifdef CONFIG_BOOKE
 142         /* BookE base exception scratch space; align on cacheline */
 143         unsigned long   normsave[8] ____cacheline_aligned;
 144 #endif
 145 #ifdef CONFIG_PPC32
 146         void            *pgdir;         /* root of page-table tree */
 147         unsigned long   ksp_limit;      /* if ksp <= ksp_limit stack overflow */
 148 #ifdef CONFIG_PPC_RTAS
 149         unsigned long   rtas_sp;        /* stack pointer for when in RTAS */
 150 #endif
 151 #endif
 152 #if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP)
 153         unsigned long   kuap;           /* opened segments for user access */
 154 #endif
 155 #ifdef CONFIG_VMAP_STACK
 156         unsigned long   srr0;
 157         unsigned long   srr1;
 158         unsigned long   dar;
 159         unsigned long   dsisr;
 160 #ifdef CONFIG_PPC_BOOK3S_32
 161         unsigned long   r0, r3, r4, r5, r6, r8, r9, r11;
 162         unsigned long   lr, ctr;
 163 #endif
 164 #endif
 165         /* Debug Registers */
 166         struct debug_reg debug;
 167 #ifdef CONFIG_PPC_FPU_REGS
 168         struct thread_fp_state  fp_state;
 169         struct thread_fp_state  *fp_save_area;
 170 #endif
 171         int             fpexc_mode;     /* floating-point exception mode */
 172         unsigned int    align_ctl;      /* alignment handling control */
 173 #ifdef CONFIG_HAVE_HW_BREAKPOINT
 174         struct perf_event *ptrace_bps[HBP_NUM_MAX];
 175         /*
 176          * Helps identify source of single-step exception and subsequent
 177          * hw-breakpoint enablement
 178          */
 179         struct perf_event *last_hit_ubp[HBP_NUM_MAX];
 180 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
 181         struct arch_hw_breakpoint hw_brk[HBP_NUM_MAX]; /* hardware breakpoint info */
 182         unsigned long   trap_nr;        /* last trap # on this thread */
 183         u8 load_slb;                    /* Ages out SLB preload cache entries */
 184         u8 load_fp;
 185 #ifdef CONFIG_ALTIVEC
 186         u8 load_vec;
 187         struct thread_vr_state vr_state;
 188         struct thread_vr_state *vr_save_area;
 189         unsigned long   vrsave;
 190         int             used_vr;        /* set if process has used altivec */
 191 #endif /* CONFIG_ALTIVEC */
 192 #ifdef CONFIG_VSX
 193         /* VSR status */
 194         int             used_vsr;       /* set if process has used VSX */
 195 #endif /* CONFIG_VSX */
 196 #ifdef CONFIG_SPE
 197         unsigned long   evr[32];        /* upper 32-bits of SPE regs */
 198         u64             acc;            /* Accumulator */
 199         unsigned long   spefscr;        /* SPE & eFP status */
 200         unsigned long   spefscr_last;   /* SPEFSCR value on last prctl
 201                                            call or trap return */
 202         int             used_spe;       /* set if process has used spe */
 203 #endif /* CONFIG_SPE */
 204 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 205         u8      load_tm;
 206         u64             tm_tfhar;       /* Transaction fail handler addr */
 207         u64             tm_texasr;      /* Transaction exception & summary */
 208         u64             tm_tfiar;       /* Transaction fail instr address reg */
 209         struct pt_regs  ckpt_regs;      /* Checkpointed registers */
 210
 211         unsigned long   tm_tar;
 212         unsigned long   tm_ppr;
 213         unsigned long   tm_dscr;
 214         unsigned long   tm_amr;
 215
 216         /*
 217          * Checkpointed FP and VSX 0-31 register set.
 218          *
 219          * When a transaction is active/signalled/scheduled etc., *regs is the
 220          * most recent set of/speculated GPRs with ckpt_regs being the older
 221          * checkpointed regs to which we roll back if transaction aborts.
 222          *
 223          * These are analogous to how ckpt_regs and pt_regs work
 224          */
 225         struct thread_fp_state ckfp_state; /* Checkpointed FP state */
 226         struct thread_vr_state ckvr_state; /* Checkpointed VR state */
 227         unsigned long   ckvrsave; /* Checkpointed VRSAVE */
 228 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 229 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER
 230         void*           kvm_shadow_vcpu; /* KVM internal data */
 231 #endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
 232 #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
 233         struct kvm_vcpu *kvm_vcpu;
 234 #endif
 235 #ifdef CONFIG_PPC64
 236         unsigned long   dscr;
 237         unsigned long   fscr;
 238         /*
 239          * This member element dscr_inherit indicates that the process
 240          * has explicitly attempted and changed the DSCR register value
 241          * for itself. Hence kernel wont use the default CPU DSCR value
 242          * contained in the PACA structure anymore during process context
 243          * switch. Once this variable is set, this behaviour will also be
 244          * inherited to all the children of this process from that point
 245          * onwards.
 246          */
 247         int             dscr_inherit;
 248         unsigned long   tidr;
 249 #endif
 250 #ifdef CONFIG_PPC_BOOK3S_64
 251         unsigned long   tar;
 252         unsigned long   ebbrr;
 253         unsigned long   ebbhr;
 254         unsigned long   bescr;
 255         unsigned long   siar;
 256         unsigned long   sdar;
 257         unsigned long   sier;
 258         unsigned long   mmcr2;
 259         unsigned        mmcr0;
 260
 261         unsigned        used_ebb;
 262         unsigned long   mmcr3;
 263         unsigned long   sier2;
 264         unsigned long   sier3;
 265
 266 #endif
 267 };
 268
 269 #define ARCH_MIN_TASKALIGN 16
 270
 271 #define INIT_SP         (sizeof(init_stack) + (unsigned long) &init_stack)
 272 #define INIT_SP_LIMIT   ((unsigned long)&init_stack)
 273
 274 #ifdef CONFIG_SPE
 275 #define SPEFSCR_INIT \
 276         .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE, \
 277         .spefscr_last = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
 278 #else
 279 #define SPEFSCR_INIT
 280 #endif
 281
 282 #ifdef CONFIG_PPC32
 283 #define INIT_THREAD { \
 284         .ksp = INIT_SP, \
 285         .ksp_limit = INIT_SP_LIMIT, \
 286         .pgdir = swapper_pg_dir, \
 287         .fpexc_mode = MSR_FE0 | MSR_FE1, \
 288         SPEFSCR_INIT \
 289 }
 290 #else
 291 #define INIT_THREAD  { \
 292         .ksp = INIT_SP, \
 293         .fpexc_mode = 0, \
 294 }
 295 #endif
 296
 297 #define task_pt_regs(tsk)       ((tsk)->thread.regs)
 298
 299 unsigned long get_wchan(struct task_struct *p);
 300
 301 #define KSTK_EIP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
 302 #define KSTK_ESP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
 303
 304 /* Get/set floating-point exception mode */
 305 #define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
 306 #define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
 307
 308 extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
 309 extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
 310
 311 #define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
 312 #define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
 313
 314 extern int get_endian(struct task_struct *tsk, unsigned long adr);
 315 extern int set_endian(struct task_struct *tsk, unsigned int val);
 316
 317 #define GET_UNALIGN_CTL(tsk, adr)       get_unalign_ctl((tsk), (adr))
 318 #define SET_UNALIGN_CTL(tsk, val)       set_unalign_ctl((tsk), (val))
 319
 320 extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
 321 extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
 322
 323 extern void load_fp_state(struct thread_fp_state *fp);
 324 extern void store_fp_state(struct thread_fp_state *fp);
 325 extern void load_vr_state(struct thread_vr_state *vr);
 326 extern void store_vr_state(struct thread_vr_state *vr);
 327
 328 static inline unsigned int __unpack_fe01(unsigned long msr_bits)
 329 {
 330         return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
 331 }
 332
 333 static inline unsigned long __pack_fe01(unsigned int fpmode)
 334 {
 335         return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
 336 }
 337
 338 #ifdef CONFIG_PPC64
 339
 340 #define spin_begin()    HMT_low()
 341
 342 #define spin_cpu_relax()        barrier()
 343
 344 #define spin_end()      HMT_medium()
 345
 346 #define spin_until_cond(cond)                                   \
 347 do {                                                            \
 348         if (unlikely(!(cond))) {                                \
 349                 spin_begin();                                   \
 350                 do {                                            \
 351                         spin_cpu_relax();                       \
 352                 } while (!(cond));                              \
 353                 spin_end();                                     \
 354         }                                                       \
 355 } while (0)
 356
 357 #endif
 358
 359 /* Check that a certain kernel stack pointer is valid in task_struct p */
 360 int validate_sp(unsigned long sp, struct task_struct *p,
 361                        unsigned long nbytes);
 362
 363 /*
 364  * Prefetch macros.
 365  */
 366 #define ARCH_HAS_PREFETCH
 367 #define ARCH_HAS_PREFETCHW
 368 #define ARCH_HAS_SPINLOCK_PREFETCH
 369
 370 static inline void prefetch(const void *x)
 371 {
 372         if (unlikely(!x))
 373                 return;
 374
 375         __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
 376 }
 377
 378 static inline void prefetchw(const void *x)
 379 {
 380         if (unlikely(!x))
 381                 return;
 382
 383         __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
 384 }
 385
 386 #define spin_lock_prefetch(x)   prefetchw(x)
 387
 388 #define HAVE_ARCH_PICK_MMAP_LAYOUT
 389
 390 /* asm stubs */
 391 extern unsigned long isa300_idle_stop_noloss(unsigned long psscr_val);
 392 extern unsigned long isa300_idle_stop_mayloss(unsigned long psscr_val);
 393 extern unsigned long isa206_idle_insn_mayloss(unsigned long type);
 394 #ifdef CONFIG_PPC_970_NAP
 395 extern void power4_idle_nap(void);
 396 #endif
 397
 398 extern unsigned long cpuidle_disable;
 399 enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
 400
 401 extern int powersave_nap;       /* set if nap mode can be used in idle loop */
 402
 403 extern void power7_idle_type(unsigned long type);
 404 extern void arch300_idle_type(unsigned long stop_psscr_val,
 405                               unsigned long stop_psscr_mask);
 406
 407 extern int fix_alignment(struct pt_regs *);
 408
 409 #ifdef CONFIG_PPC64
 410 /*
 411  * We handle most unaligned accesses in hardware. On the other hand
 412  * unaligned DMA can be very expensive on some ppc64 IO chips (it does
 413  * powers of 2 writes until it reaches sufficient alignment).
 414  *
 415  * Based on this we disable the IP header alignment in network drivers.
 416  */
 417 #define NET_IP_ALIGN    0
 418 #endif
 419
 420 #endif /* __KERNEL__ */
 421 #endif /* __ASSEMBLY__ */
 422 #endif /* _ASM_POWERPC_PROCESSOR_H */