arch/powerpc/mm/mem.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  PowerPC version
   4  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   5  *
   6  *  Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
   7  *  and Cort Dougan (PReP) (cort@cs.nmt.edu)
   8  *    Copyright (C) 1996 Paul Mackerras
   9  *  PPC44x/36-bit changes by Matt Porter (mporter@mvista.com)
  10  *
  11  *  Derived from "arch/i386/mm/init.c"
  12  *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
  13  */
  14
  15 #include <linux/export.h>
  16 #include <linux/sched.h>
  17 #include <linux/kernel.h>
  18 #include <linux/errno.h>
  19 #include <linux/string.h>
  20 #include <linux/gfp.h>
  21 #include <linux/types.h>
  22 #include <linux/mm.h>
  23 #include <linux/stddef.h>
  24 #include <linux/init.h>
  25 #include <linux/memblock.h>
  26 #include <linux/highmem.h>
  27 #include <linux/initrd.h>
  28 #include <linux/pagemap.h>
  29 #include <linux/suspend.h>
  30 #include <linux/hugetlb.h>
  31 #include <linux/slab.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/memremap.h>
  34 #include <linux/dma-direct.h>
  35 #include <linux/kprobes.h>
  36
  37 #include <asm/prom.h>
  38 #include <asm/io.h>
  39 #include <asm/mmu_context.h>
  40 #include <asm/mmu.h>
  41 #include <asm/smp.h>
  42 #include <asm/machdep.h>
  43 #include <asm/btext.h>
  44 #include <asm/tlb.h>
  45 #include <asm/sections.h>
  46 #include <asm/sparsemem.h>
  47 #include <asm/vdso.h>
  48 #include <asm/fixmap.h>
  49 #include <asm/swiotlb.h>
  50 #include <asm/rtas.h>
  51 #include <asm/kasan.h>
  52 #include <asm/svm.h>
  53 #include <asm/mmzone.h>
  54
  55 #include <mm/mmu_decl.h>
  56
  57 static DEFINE_MUTEX(linear_mapping_mutex);
  58 unsigned long long memory_limit;
  59 bool init_mem_is_free;
  60
  61 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
  62                               unsigned long size, pgprot_t vma_prot)
  63 {
  64         if (ppc_md.phys_mem_access_prot)
  65                 return ppc_md.phys_mem_access_prot(file, pfn, size, vma_prot);
  66
  67         if (!page_is_ram(pfn))
  68                 vma_prot = pgprot_noncached(vma_prot);
  69
  70         return vma_prot;
  71 }
  72 EXPORT_SYMBOL(phys_mem_access_prot);
  73
  74 #ifdef CONFIG_MEMORY_HOTPLUG
  75
  76 #ifdef CONFIG_NUMA
  77 int memory_add_physaddr_to_nid(u64 start)
  78 {
  79         return hot_add_scn_to_nid(start);
  80 }
  81 #endif
  82
  83 int __weak create_section_mapping(unsigned long start, unsigned long end,
  84                                   int nid, pgprot_t prot)
  85 {
  86         return -ENODEV;
  87 }
  88
  89 int __weak remove_section_mapping(unsigned long start, unsigned long end)
  90 {
  91         return -ENODEV;
  92 }
  93
  94 #define FLUSH_CHUNK_SIZE SZ_1G
  95 /**
  96  * flush_dcache_range_chunked(): Write any modified data cache blocks out to
  97  * memory and invalidate them, in chunks of up to FLUSH_CHUNK_SIZE
  98  * Does not invalidate the corresponding instruction cache blocks.
  99  *
 100  * @start: the start address
 101  * @stop: the stop address (exclusive)
 102  * @chunk: the max size of the chunks
 103  */
 104 static void flush_dcache_range_chunked(unsigned long start, unsigned long stop,
 105                                        unsigned long chunk)
 106 {
 107         unsigned long i;
 108
 109         for (i = start; i < stop; i += chunk) {
 110                 flush_dcache_range(i, min(stop, i + chunk));
 111                 cond_resched();
 112         }
 113 }
 114
 115 int __ref arch_create_linear_mapping(int nid, u64 start, u64 size,
 116                                      struct mhp_params *params)
 117 {
 118         int rc;
 119
 120         start = (unsigned long)__va(start);
 121         mutex_lock(&linear_mapping_mutex);
 122         rc = create_section_mapping(start, start + size, nid,
 123                                     params->pgprot);
 124         mutex_unlock(&linear_mapping_mutex);
 125         if (rc) {
 126                 pr_warn("Unable to create linear mapping for 0x%llx..0x%llx: %d\n",
 127                         start, start + size, rc);
 128                 return -EFAULT;
 129         }
 130         return 0;
 131 }
 132
 133 void __ref arch_remove_linear_mapping(u64 start, u64 size)
 134 {
 135         int ret;
 136
 137         /* Remove htab bolted mappings for this section of memory */
 138         start = (unsigned long)__va(start);
 139         flush_dcache_range_chunked(start, start + size, FLUSH_CHUNK_SIZE);
 140
 141         mutex_lock(&linear_mapping_mutex);
 142         ret = remove_section_mapping(start, start + size);
 143         mutex_unlock(&linear_mapping_mutex);
 144         if (ret)
 145                 pr_warn("Unable to remove linear mapping for 0x%llx..0x%llx: %d\n",
 146                         start, start + size, ret);
 147
 148         /* Ensure all vmalloc mappings are flushed in case they also
 149          * hit that section of memory
 150          */
 151         vm_unmap_aliases();
 152 }
 153
 154 int __ref arch_add_memory(int nid, u64 start, u64 size,
 155                           struct mhp_params *params)
 156 {
 157         unsigned long start_pfn = start >> PAGE_SHIFT;
 158         unsigned long nr_pages = size >> PAGE_SHIFT;
 159         int rc;
 160
 161         rc = arch_create_linear_mapping(nid, start, size, params);
 162         if (rc)
 163                 return rc;
 164         rc = __add_pages(nid, start_pfn, nr_pages, params);
 165         if (rc)
 166                 arch_remove_linear_mapping(start, size);
 167         return rc;
 168 }
 169
 170 void __ref arch_remove_memory(int nid, u64 start, u64 size,
 171                               struct vmem_altmap *altmap)
 172 {
 173         unsigned long start_pfn = start >> PAGE_SHIFT;
 174         unsigned long nr_pages = size >> PAGE_SHIFT;
 175
 176         __remove_pages(start_pfn, nr_pages, altmap);
 177         arch_remove_linear_mapping(start, size);
 178 }
 179 #endif
 180
 181 #ifndef CONFIG_NEED_MULTIPLE_NODES
 182 void __init mem_topology_setup(void)
 183 {
 184         max_low_pfn = max_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
 185         min_low_pfn = MEMORY_START >> PAGE_SHIFT;
 186 #ifdef CONFIG_HIGHMEM
 187         max_low_pfn = lowmem_end_addr >> PAGE_SHIFT;
 188 #endif
 189
 190         /* Place all memblock_regions in the same node and merge contiguous
 191          * memblock_regions
 192          */
 193         memblock_set_node(0, PHYS_ADDR_MAX, &memblock.memory, 0);
 194 }
 195
 196 void __init initmem_init(void)
 197 {
 198         sparse_init();
 199 }
 200
 201 /* mark pages that don't exist as nosave */
 202 static int __init mark_nonram_nosave(void)
 203 {
 204         unsigned long spfn, epfn, prev = 0;
 205         int i;
 206
 207         for_each_mem_pfn_range(i, MAX_NUMNODES, &spfn, &epfn, NULL) {
 208                 if (prev && prev < spfn)
 209                         register_nosave_region(prev, spfn);
 210
 211                 prev = epfn;
 212         }
 213
 214         return 0;
 215 }
 216 #else /* CONFIG_NEED_MULTIPLE_NODES */
 217 static int __init mark_nonram_nosave(void)
 218 {
 219         return 0;
 220 }
 221 #endif
 222
 223 /*
 224  * Zones usage:
 225  *
 226  * We setup ZONE_DMA to be 31-bits on all platforms and ZONE_NORMAL to be
 227  * everything else. GFP_DMA32 page allocations automatically fall back to
 228  * ZONE_DMA.
 229  *
 230  * By using 31-bit unconditionally, we can exploit zone_dma_bits to inform the
 231  * generic DMA mapping code.  32-bit only devices (if not handled by an IOMMU
 232  * anyway) will take a first dip into ZONE_NORMAL and get otherwise served by
 233  * ZONE_DMA.
 234  */
 235 static unsigned long max_zone_pfns[MAX_NR_ZONES];
 236
 237 /*
 238  * paging_init() sets up the page tables - in fact we've already done this.
 239  */
 240 void __init paging_init(void)
 241 {
 242         unsigned long long total_ram = memblock_phys_mem_size();
 243         phys_addr_t top_of_ram = memblock_end_of_DRAM();
 244
 245 #ifdef CONFIG_HIGHMEM
 246         unsigned long v = __fix_to_virt(FIX_KMAP_END);
 247         unsigned long end = __fix_to_virt(FIX_KMAP_BEGIN);
 248
 249         for (; v < end; v += PAGE_SIZE)
 250                 map_kernel_page(v, 0, __pgprot(0)); /* XXX gross */
 251
 252         map_kernel_page(PKMAP_BASE, 0, __pgprot(0));    /* XXX gross */
 253         pkmap_page_table = virt_to_kpte(PKMAP_BASE);
 254 #endif /* CONFIG_HIGHMEM */
 255
 256         printk(KERN_DEBUG "Top of RAM: 0x%llx, Total RAM: 0x%llx\n",
 257                (unsigned long long)top_of_ram, total_ram);
 258         printk(KERN_DEBUG "Memory hole size: %ldMB\n",
 259                (long int)((top_of_ram - total_ram) >> 20));
 260
 261         /*
 262          * Allow 30-bit DMA for very limited Broadcom wifi chips on many
 263          * powerbooks.
 264          */
 265         if (IS_ENABLED(CONFIG_PPC32))
 266                 zone_dma_bits = 30;
 267         else
 268                 zone_dma_bits = 31;
 269
 270 #ifdef CONFIG_ZONE_DMA
 271         max_zone_pfns[ZONE_DMA] = min(max_low_pfn,
 272                                       1UL << (zone_dma_bits - PAGE_SHIFT));
 273 #endif
 274         max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
 275 #ifdef CONFIG_HIGHMEM
 276         max_zone_pfns[ZONE_HIGHMEM] = max_pfn;
 277 #endif
 278
 279         free_area_init(max_zone_pfns);
 280
 281         mark_nonram_nosave();
 282 }
 283
 284 void __init mem_init(void)
 285 {
 286         /*
 287          * book3s is limited to 16 page sizes due to encoding this in
 288          * a 4-bit field for slices.
 289          */
 290         BUILD_BUG_ON(MMU_PAGE_COUNT > 16);
 291
 292 #ifdef CONFIG_SWIOTLB
 293         /*
 294          * Some platforms (e.g. 85xx) limit DMA-able memory way below
 295          * 4G. We force memblock to bottom-up mode to ensure that the
 296          * memory allocated in swiotlb_init() is DMA-able.
 297          * As it's the last memblock allocation, no need to reset it
 298          * back to to-down.
 299          */
 300         memblock_set_bottom_up(true);
 301         if (is_secure_guest())
 302                 svm_swiotlb_init();
 303         else
 304                 swiotlb_init(0);
 305 #endif
 306
 307         high_memory = (void *) __va(max_low_pfn * PAGE_SIZE);
 308         set_max_mapnr(max_pfn);
 309
 310         kasan_late_init();
 311
 312         memblock_free_all();
 313
 314 #ifdef CONFIG_HIGHMEM
 315         {
 316                 unsigned long pfn, highmem_mapnr;
 317
 318                 highmem_mapnr = lowmem_end_addr >> PAGE_SHIFT;
 319                 for (pfn = highmem_mapnr; pfn < max_mapnr; ++pfn) {
 320                         phys_addr_t paddr = (phys_addr_t)pfn << PAGE_SHIFT;
 321                         struct page *page = pfn_to_page(pfn);
 322                         if (!memblock_is_reserved(paddr))
 323                                 free_highmem_page(page);
 324                 }
 325         }
 326 #endif /* CONFIG_HIGHMEM */
 327
 328 #if defined(CONFIG_PPC_FSL_BOOK3E) && !defined(CONFIG_SMP)
 329         /*
 330          * If smp is enabled, next_tlbcam_idx is initialized in the cpu up
 331          * functions.... do it here for the non-smp case.
 332          */
 333         per_cpu(next_tlbcam_idx, smp_processor_id()) =
 334                 (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1;
 335 #endif
 336
 337         mem_init_print_info(NULL);
 338 #ifdef CONFIG_PPC32
 339         pr_info("Kernel virtual memory layout:\n");
 340 #ifdef CONFIG_KASAN
 341         pr_info("  * 0x%08lx..0x%08lx  : kasan shadow mem\n",
 342                 KASAN_SHADOW_START, KASAN_SHADOW_END);
 343 #endif
 344         pr_info("  * 0x%08lx..0x%08lx  : fixmap\n", FIXADDR_START, FIXADDR_TOP);
 345 #ifdef CONFIG_HIGHMEM
 346         pr_info("  * 0x%08lx..0x%08lx  : highmem PTEs\n",
 347                 PKMAP_BASE, PKMAP_ADDR(LAST_PKMAP));
 348 #endif /* CONFIG_HIGHMEM */
 349         if (ioremap_bot != IOREMAP_TOP)
 350                 pr_info("  * 0x%08lx..0x%08lx  : early ioremap\n",
 351                         ioremap_bot, IOREMAP_TOP);
 352         pr_info("  * 0x%08lx..0x%08lx  : vmalloc & ioremap\n",
 353                 VMALLOC_START, VMALLOC_END);
 354 #endif /* CONFIG_PPC32 */
 355 }
 356
 357 void free_initmem(void)
 358 {
 359         ppc_md.progress = ppc_printk_progress;
 360         mark_initmem_nx();
 361         init_mem_is_free = true;
 362         free_initmem_default(POISON_FREE_INITMEM);
 363 }
 364
 365 /**
 366  * flush_coherent_icache() - if a CPU has a coherent icache, flush it
 367  * @addr: The base address to use (can be any valid address, the whole cache will be flushed)
 368  * Return true if the cache was flushed, false otherwise
 369  */
 370 static inline bool flush_coherent_icache(unsigned long addr)
 371 {
 372         /*
 373          * For a snooping icache, we still need a dummy icbi to purge all the
 374          * prefetched instructions from the ifetch buffers. We also need a sync
 375          * before the icbi to order the the actual stores to memory that might
 376          * have modified instructions with the icbi.
 377          */
 378         if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) {
 379                 mb(); /* sync */
 380                 allow_read_from_user((const void __user *)addr, L1_CACHE_BYTES);
 381                 icbi((void *)addr);
 382                 prevent_read_from_user((const void __user *)addr, L1_CACHE_BYTES);
 383                 mb(); /* sync */
 384                 isync();
 385                 return true;
 386         }
 387
 388         return false;
 389 }
 390
 391 /**
 392  * invalidate_icache_range() - Flush the icache by issuing icbi across an address range
 393  * @start: the start address
 394  * @stop: the stop address (exclusive)
 395  */
 396 static void invalidate_icache_range(unsigned long start, unsigned long stop)
 397 {
 398         unsigned long shift = l1_icache_shift();
 399         unsigned long bytes = l1_icache_bytes();
 400         char *addr = (char *)(start & ~(bytes - 1));
 401         unsigned long size = stop - (unsigned long)addr + (bytes - 1);
 402         unsigned long i;
 403
 404         for (i = 0; i < size >> shift; i++, addr += bytes)
 405                 icbi(addr);
 406
 407         mb(); /* sync */
 408         isync();
 409 }
 410
 411 /**
 412  * flush_icache_range: Write any modified data cache blocks out to memory
 413  * and invalidate the corresponding blocks in the instruction cache
 414  *
 415  * Generic code will call this after writing memory, before executing from it.
 416  *
 417  * @start: the start address
 418  * @stop: the stop address (exclusive)
 419  */
 420 void flush_icache_range(unsigned long start, unsigned long stop)
 421 {
 422         if (flush_coherent_icache(start))
 423                 return;
 424
 425         clean_dcache_range(start, stop);
 426
 427         if (IS_ENABLED(CONFIG_44x)) {
 428                 /*
 429                  * Flash invalidate on 44x because we are passed kmapped
 430                  * addresses and this doesn't work for userspace pages due to
 431                  * the virtually tagged icache.
 432                  */
 433                 iccci((void *)start);
 434                 mb(); /* sync */
 435                 isync();
 436         } else
 437                 invalidate_icache_range(start, stop);
 438 }
 439 EXPORT_SYMBOL(flush_icache_range);
 440
 441 #if !defined(CONFIG_PPC_8xx) && !defined(CONFIG_PPC64)
 442 /**
 443  * flush_dcache_icache_phys() - Flush a page by it's physical address
 444  * @physaddr: the physical address of the page
 445  */
 446 static void flush_dcache_icache_phys(unsigned long physaddr)
 447 {
 448         unsigned long bytes = l1_dcache_bytes();
 449         unsigned long nb = PAGE_SIZE / bytes;
 450         unsigned long addr = physaddr & PAGE_MASK;
 451         unsigned long msr, msr0;
 452         unsigned long loop1 = addr, loop2 = addr;
 453
 454         msr0 = mfmsr();
 455         msr = msr0 & ~MSR_DR;
 456         /*
 457          * This must remain as ASM to prevent potential memory accesses
 458          * while the data MMU is disabled
 459          */
 460         asm volatile(
 461                 "   mtctr %2;\n"
 462                 "   mtmsr %3;\n"
 463                 "   isync;\n"
 464                 "0: dcbst   0, %0;\n"
 465                 "   addi    %0, %0, %4;\n"
 466                 "   bdnz    0b;\n"
 467                 "   sync;\n"
 468                 "   mtctr %2;\n"
 469                 "1: icbi    0, %1;\n"
 470                 "   addi    %1, %1, %4;\n"
 471                 "   bdnz    1b;\n"
 472                 "   sync;\n"
 473                 "   mtmsr %5;\n"
 474                 "   isync;\n"
 475                 : "+&r" (loop1), "+&r" (loop2)
 476                 : "r" (nb), "r" (msr), "i" (bytes), "r" (msr0)
 477                 : "ctr", "memory");
 478 }
 479 NOKPROBE_SYMBOL(flush_dcache_icache_phys)
 480 #endif // !defined(CONFIG_PPC_8xx) && !defined(CONFIG_PPC64)
 481
 482 /*
 483  * This is called when a page has been modified by the kernel.
 484  * It just marks the page as not i-cache clean.  We do the i-cache
 485  * flush later when the page is given to a user process, if necessary.
 486  */
 487 void flush_dcache_page(struct page *page)
 488 {
 489         if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
 490                 return;
 491         /* avoid an atomic op if possible */
 492         if (test_bit(PG_arch_1, &page->flags))
 493                 clear_bit(PG_arch_1, &page->flags);
 494 }
 495 EXPORT_SYMBOL(flush_dcache_page);
 496
 497 void flush_dcache_icache_page(struct page *page)
 498 {
 499 #ifdef CONFIG_HUGETLB_PAGE
 500         if (PageCompound(page)) {
 501                 flush_dcache_icache_hugepage(page);
 502                 return;
 503         }
 504 #endif
 505 #if defined(CONFIG_PPC_8xx) || defined(CONFIG_PPC64)
 506         /* On 8xx there is no need to kmap since highmem is not supported */
 507         __flush_dcache_icache(page_address(page));
 508 #else
 509         if (IS_ENABLED(CONFIG_BOOKE) || sizeof(phys_addr_t) > sizeof(void *)) {
 510                 void *start = kmap_atomic(page);
 511                 __flush_dcache_icache(start);
 512                 kunmap_atomic(start);
 513         } else {
 514                 unsigned long addr = page_to_pfn(page) << PAGE_SHIFT;
 515
 516                 if (flush_coherent_icache(addr))
 517                         return;
 518                 flush_dcache_icache_phys(addr);
 519         }
 520 #endif
 521 }
 522 EXPORT_SYMBOL(flush_dcache_icache_page);
 523
 524 /**
 525  * __flush_dcache_icache(): Flush a particular page from the data cache to RAM.
 526  * Note: this is necessary because the instruction cache does *not*
 527  * snoop from the data cache.
 528  *
 529  * @page: the address of the page to flush
 530  */
 531 void __flush_dcache_icache(void *p)
 532 {
 533         unsigned long addr = (unsigned long)p;
 534
 535         if (flush_coherent_icache(addr))
 536                 return;
 537
 538         clean_dcache_range(addr, addr + PAGE_SIZE);
 539
 540         /*
 541          * We don't flush the icache on 44x. Those have a virtual icache and we
 542          * don't have access to the virtual address here (it's not the page
 543          * vaddr but where it's mapped in user space). The flushing of the
 544          * icache on these is handled elsewhere, when a change in the address
 545          * space occurs, before returning to user space.
 546          */
 547
 548         if (mmu_has_feature(MMU_FTR_TYPE_44x))
 549                 return;
 550
 551         invalidate_icache_range(addr, addr + PAGE_SIZE);
 552 }
 553
 554 void clear_user_page(void *page, unsigned long vaddr, struct page *pg)
 555 {
 556         clear_page(page);
 557
 558         /*
 559          * We shouldn't have to do this, but some versions of glibc
 560          * require it (ld.so assumes zero filled pages are icache clean)
 561          * - Anton
 562          */
 563         flush_dcache_page(pg);
 564 }
 565 EXPORT_SYMBOL(clear_user_page);
 566
 567 void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
 568                     struct page *pg)
 569 {
 570         copy_page(vto, vfrom);
 571
 572         /*
 573          * We should be able to use the following optimisation, however
 574          * there are two problems.
 575          * Firstly a bug in some versions of binutils meant PLT sections
 576          * were not marked executable.
 577          * Secondly the first word in the GOT section is blrl, used
 578          * to establish the GOT address. Until recently the GOT was
 579          * not marked executable.
 580          * - Anton
 581          */
 582 #if 0
 583         if (!vma->vm_file && ((vma->vm_flags & VM_EXEC) == 0))
 584                 return;
 585 #endif
 586
 587         flush_dcache_page(pg);
 588 }
 589
 590 void flush_icache_user_page(struct vm_area_struct *vma, struct page *page,
 591                              unsigned long addr, int len)
 592 {
 593         unsigned long maddr;
 594
 595         maddr = (unsigned long) kmap(page) + (addr & ~PAGE_MASK);
 596         flush_icache_range(maddr, maddr + len);
 597         kunmap(page);
 598 }
 599
 600 /*
 601  * System memory should not be in /proc/iomem but various tools expect it
 602  * (eg kdump).
 603  */
 604 static int __init add_system_ram_resources(void)
 605 {
 606         phys_addr_t start, end;
 607         u64 i;
 608
 609         for_each_mem_range(i, &start, &end) {
 610                 struct resource *res;
 611
 612                 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
 613                 WARN_ON(!res);
 614
 615                 if (res) {
 616                         res->name = "System RAM";
 617                         res->start = start;
 618                         /*
 619                          * In memblock, end points to the first byte after
 620                          * the range while in resourses, end points to the
 621                          * last byte in the range.
 622                          */
 623                         res->end = end - 1;
 624                         res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY;
 625                         WARN_ON(request_resource(&iomem_resource, res) < 0);
 626                 }
 627         }
 628
 629         return 0;
 630 }
 631 subsys_initcall(add_system_ram_resources);
 632
 633 #ifdef CONFIG_STRICT_DEVMEM
 634 /*
 635  * devmem_is_allowed(): check to see if /dev/mem access to a certain address
 636  * is valid. The argument is a physical page number.
 637  *
 638  * Access has to be given to non-kernel-ram areas as well, these contain the
 639  * PCI mmio resources as well as potential bios/acpi data regions.
 640  */
 641 int devmem_is_allowed(unsigned long pfn)
 642 {
 643         if (page_is_rtas_user_buf(pfn))
 644                 return 1;
 645         if (iomem_is_exclusive(PFN_PHYS(pfn)))
 646                 return 0;
 647         if (!page_is_ram(pfn))
 648                 return 1;
 649         return 0;
 650 }
 651 #endif /* CONFIG_STRICT_DEVMEM */
 652
 653 /*
 654  * This is defined in kernel/resource.c but only powerpc needs to export it, for
 655  * the EHEA driver. Drop this when drivers/net/ethernet/ibm/ehea is removed.
 656  */
 657 EXPORT_SYMBOL_GPL(walk_system_ram_range);