arch/riscv/include/uapi/asm/unistd.h

   1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
   2 /*
   3  * Copyright (C) 2018 David Abdurachmanov <david.abdurachmanov@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <https://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifdef __LP64__
  19 #define __ARCH_WANT_NEW_STAT
  20 #define __ARCH_WANT_SET_GET_RLIMIT
  21 #define __ARCH_WANT_SYS_CLONE3
  22 #endif /* __LP64__ */
  23
  24 #include <asm-generic/unistd.h>
  25
  26 /*
  27  * Allows the instruction cache to be flushed from userspace.  Despite RISC-V
  28  * having a direct 'fence.i' instruction available to userspace (which we
  29  * can't trap!), that's not actually viable when running on Linux because the
  30  * kernel might schedule a process on another hart.  There is no way for
  31  * userspace to handle this without invoking the kernel (as it doesn't know the
  32  * thread->hart mappings), so we've defined a RISC-V specific system call to
  33  * flush the instruction cache.
  34  *
  35  * __NR_riscv_flush_icache is defined to flush the instruction cache over an
  36  * address range, with the flush applying to either all threads or just the
  37  * caller.  We don't currently do anything with the address range, that's just
  38  * in there for forwards compatibility.
  39  */
  40 #ifndef __NR_riscv_flush_icache
  41 #define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15)
  42 #endif
  43 __SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache)