| blob | ff27a620edd808add83812804db2242efd70acd9 |
1 [
2 {
3 "PublicDescription": "Demand Data Read requests that hit L2 cache.",
4 "EventCode": "0x24",
5 "Counter": "0,1,2,3",
6 "UMask": "0x1",
7 "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
8 "SampleAfterValue": "200003",
9 "BriefDescription": "Demand Data Read requests that hit L2 cache",
10 "CounterHTOff": "0,1,2,3,4,5,6,7"
11 },
12 {
13 "PublicDescription": "RFO requests that hit L2 cache.",
14 "EventCode": "0x24",
15 "Counter": "0,1,2,3",
16 "UMask": "0x4",
17 "EventName": "L2_RQSTS.RFO_HIT",
18 "SampleAfterValue": "200003",
19 "BriefDescription": "RFO requests that hit L2 cache",
20 "CounterHTOff": "0,1,2,3,4,5,6,7"
21 },
22 {
23 "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
24 "EventCode": "0x24",
25 "Counter": "0,1,2,3",
26 "UMask": "0x8",
27 "EventName": "L2_RQSTS.RFO_MISS",
28 "SampleAfterValue": "200003",
29 "BriefDescription": "RFO requests that miss L2 cache",
30 "CounterHTOff": "0,1,2,3,4,5,6,7"
31 },
32 {
33 "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
34 "EventCode": "0x24",
35 "Counter": "0,1,2,3",
36 "UMask": "0x10",
37 "EventName": "L2_RQSTS.CODE_RD_HIT",
38 "SampleAfterValue": "200003",
39 "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
40 "CounterHTOff": "0,1,2,3,4,5,6,7"
41 },
42 {
43 "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
44 "EventCode": "0x24",
45 "Counter": "0,1,2,3",
46 "UMask": "0x20",
47 "EventName": "L2_RQSTS.CODE_RD_MISS",
48 "SampleAfterValue": "200003",
49 "BriefDescription": "L2 cache misses when fetching instructions",
50 "CounterHTOff": "0,1,2,3,4,5,6,7"
51 },
52 {
53 "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
54 "EventCode": "0x24",
55 "Counter": "0,1,2,3",
56 "UMask": "0x40",
57 "EventName": "L2_RQSTS.PF_HIT",
58 "SampleAfterValue": "200003",
59 "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache",
60 "CounterHTOff": "0,1,2,3,4,5,6,7"
61 },
62 {
63 "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
64 "EventCode": "0x24",
65 "Counter": "0,1,2,3",
66 "UMask": "0x80",
67 "EventName": "L2_RQSTS.PF_MISS",
68 "SampleAfterValue": "200003",
69 "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache",
70 "CounterHTOff": "0,1,2,3,4,5,6,7"
71 },
72 {
73 "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
74 "EventCode": "0x24",
75 "Counter": "0,1,2,3",
76 "UMask": "0x3",
77 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
78 "SampleAfterValue": "200003",
79 "BriefDescription": "Demand Data Read requests",
80 "CounterHTOff": "0,1,2,3,4,5,6,7"
81 },
82 {
83 "PublicDescription": "Counts all L2 store RFO requests.",
84 "EventCode": "0x24",
85 "Counter": "0,1,2,3",
86 "UMask": "0xc",
87 "EventName": "L2_RQSTS.ALL_RFO",
88 "SampleAfterValue": "200003",
89 "BriefDescription": "RFO requests to L2 cache",
90 "CounterHTOff": "0,1,2,3,4,5,6,7"
91 },
92 {
93 "PublicDescription": "Counts all L2 code requests.",
94 "EventCode": "0x24",
95 "Counter": "0,1,2,3",
96 "UMask": "0x30",
97 "EventName": "L2_RQSTS.ALL_CODE_RD",
98 "SampleAfterValue": "200003",
99 "BriefDescription": "L2 code requests",
100 "CounterHTOff": "0,1,2,3,4,5,6,7"
101 },
102 {
103 "PublicDescription": "Counts all L2 HW prefetcher requests.",
104 "EventCode": "0x24",
105 "Counter": "0,1,2,3",
106 "UMask": "0xc0",
107 "EventName": "L2_RQSTS.ALL_PF",
108 "SampleAfterValue": "200003",
109 "BriefDescription": "Requests from L2 hardware prefetchers",
110 "CounterHTOff": "0,1,2,3,4,5,6,7"
111 },
112 {
113 "PublicDescription": "RFOs that miss cache lines.",
114 "EventCode": "0x27",
115 "Counter": "0,1,2,3",
116 "UMask": "0x1",
117 "EventName": "L2_STORE_LOCK_RQSTS.MISS",
118 "SampleAfterValue": "200003",
119 "BriefDescription": "RFOs that miss cache lines",
120 "CounterHTOff": "0,1,2,3,4,5,6,7"
121 },
122 {
123 "PublicDescription": "RFOs that hit cache lines in M state.",
124 "EventCode": "0x27",
125 "Counter": "0,1,2,3",
126 "UMask": "0x8",
127 "EventName": "L2_STORE_LOCK_RQSTS.HIT_M",
128 "SampleAfterValue": "200003",
129 "BriefDescription": "RFOs that hit cache lines in M state",
130 "CounterHTOff": "0,1,2,3,4,5,6,7"
131 },
132 {
133 "PublicDescription": "RFOs that access cache lines in any state.",
134 "EventCode": "0x27",
135 "Counter": "0,1,2,3",
136 "UMask": "0xf",
137 "EventName": "L2_STORE_LOCK_RQSTS.ALL",
138 "SampleAfterValue": "200003",
139 "BriefDescription": "RFOs that access cache lines in any state",
140 "CounterHTOff": "0,1,2,3,4,5,6,7"
141 },
142 {
143 "PublicDescription": "Not rejected writebacks that missed LLC.",
144 "EventCode": "0x28",
145 "Counter": "0,1,2,3",
146 "UMask": "0x1",
147 "EventName": "L2_L1D_WB_RQSTS.MISS",
148 "SampleAfterValue": "200003",
149 "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)",
150 "CounterHTOff": "0,1,2,3,4,5,6,7"
151 },
152 {
153 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.",
154 "EventCode": "0x28",
155 "Counter": "0,1,2,3",
156 "UMask": "0x4",
157 "EventName": "L2_L1D_WB_RQSTS.HIT_E",
158 "SampleAfterValue": "200003",
159 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state",
160 "CounterHTOff": "0,1,2,3,4,5,6,7"
161 },
162 {
163 "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.",
164 "EventCode": "0x28",
165 "Counter": "0,1,2,3",
166 "UMask": "0x8",
167 "EventName": "L2_L1D_WB_RQSTS.HIT_M",
168 "SampleAfterValue": "200003",
169 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state",
170 "CounterHTOff": "0,1,2,3,4,5,6,7"
171 },
172 {
173 "EventCode": "0x28",
174 "Counter": "0,1,2,3",
175 "UMask": "0xf",
176 "EventName": "L2_L1D_WB_RQSTS.ALL",
177 "SampleAfterValue": "200003",
178 "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.",
179 "CounterHTOff": "0,1,2,3,4,5,6,7"
180 },
181 {
182 "PublicDescription": "This event counts each cache miss condition for references to the last level cache.",
183 "EventCode": "0x2E",
184 "Counter": "0,1,2,3",
185 "UMask": "0x41",
186 "EventName": "LONGEST_LAT_CACHE.MISS",
187 "SampleAfterValue": "100003",
188 "BriefDescription": "Core-originated cacheable demand requests missed LLC",
189 "CounterHTOff": "0,1,2,3,4,5,6,7"
190 },
191 {
192 "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.",
193 "EventCode": "0x2E",
194 "Counter": "0,1,2,3",
195 "UMask": "0x4f",
196 "EventName": "LONGEST_LAT_CACHE.REFERENCE",
197 "SampleAfterValue": "100003",
198 "BriefDescription": "Core-originated cacheable demand requests that refer to LLC",
199 "CounterHTOff": "0,1,2,3,4,5,6,7"
200 },
201 {
202 "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",
203 "EventCode": "0x48",
204 "Counter": "2",
205 "UMask": "0x1",
206 "EventName": "L1D_PEND_MISS.PENDING",
207 "SampleAfterValue": "2000003",
208 "BriefDescription": "L1D miss oustandings duration in cycles",
209 "CounterHTOff": "2"
210 },
211 {
212 "EventCode": "0x48",
213 "Counter": "2",
214 "UMask": "0x1",
215 "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
216 "SampleAfterValue": "2000003",
217 "BriefDescription": "Cycles with L1D load Misses outstanding.",
218 "CounterMask": "1",
219 "CounterHTOff": "2"
220 },
221 {
222 "PublicDescription": "Counts the number of lines brought into the L1 data cache.",
223 "EventCode": "0x51",
224 "Counter": "0,1,2,3",
225 "UMask": "0x1",
226 "EventName": "L1D.REPLACEMENT",
227 "SampleAfterValue": "2000003",
228 "BriefDescription": "L1D data line replacements",
229 "CounterHTOff": "0,1,2,3,4,5,6,7"
230 },
231 {
232 "PublicDescription": "Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
233 "EventCode": "0x60",
234 "Counter": "0,1,2,3",
235 "UMask": "0x1",
236 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
237 "SampleAfterValue": "2000003",
238 "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
239 "CounterHTOff": "0,1,2,3,4,5,6,7"
240 },
241 {
242 "PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
243 "EventCode": "0x60",
244 "Counter": "0,1,2,3",
245 "UMask": "0x2",
246 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
247 "SampleAfterValue": "2000003",
248 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
249 "CounterHTOff": "0,1,2,3,4,5,6,7"
250 },
251 {
252 "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.",
253 "EventCode": "0x60",
254 "Counter": "0,1,2,3",
255 "UMask": "0x4",
256 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
257 "SampleAfterValue": "2000003",
258 "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
259 "CounterHTOff": "0,1,2,3,4,5,6,7"
260 },
261 {
262 "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
263 "EventCode": "0x60",
264 "Counter": "0,1,2,3",
265 "UMask": "0x8",
266 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
267 "SampleAfterValue": "2000003",
268 "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
269 "CounterHTOff": "0,1,2,3,4,5,6,7"
270 },
271 {
272 "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
273 "EventCode": "0x60",
274 "Counter": "0,1,2,3",
275 "UMask": "0x1",
276 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
277 "SampleAfterValue": "2000003",
278 "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
279 "CounterMask": "1",
280 "CounterHTOff": "0,1,2,3,4,5,6,7"
281 },
282 {
283 "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
284 "EventCode": "0x60",
285 "Counter": "0,1,2,3",
286 "UMask": "0x8",
287 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
288 "SampleAfterValue": "2000003",
289 "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
290 "CounterMask": "1",
291 "CounterHTOff": "0,1,2,3,4,5,6,7"
292 },
293 {
294 "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
295 "EventCode": "0x60",
296 "Counter": "0,1,2,3",
297 "UMask": "0x2",
298 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
299 "SampleAfterValue": "2000003",
300 "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
301 "CounterMask": "1",
302 "CounterHTOff": "0,1,2,3,4,5,6,7"
303 },
304 {
305 "PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
306 "EventCode": "0x60",
307 "Counter": "0,1,2,3",
308 "UMask": "0x4",
309 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
310 "SampleAfterValue": "2000003",
311 "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
312 "CounterMask": "1",
313 "CounterHTOff": "0,1,2,3,4,5,6,7"
314 },
315 {
316 "PublicDescription": "Cycles in which the L1D is locked.",
317 "EventCode": "0x63",
318 "Counter": "0,1,2,3",
319 "UMask": "0x2",
320 "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
321 "SampleAfterValue": "2000003",
322 "BriefDescription": "Cycles when L1D is locked",
323 "CounterHTOff": "0,1,2,3,4,5,6,7"
324 },
325 {
326 "PublicDescription": "Demand data read requests sent to uncore.",
327 "EventCode": "0xB0",
328 "Counter": "0,1,2,3",
329 "UMask": "0x1",
330 "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
331 "SampleAfterValue": "100003",
332 "BriefDescription": "Demand Data Read requests sent to uncore",
333 "CounterHTOff": "0,1,2,3,4,5,6,7"
334 },
335 {
336 "PublicDescription": "Demand code read requests sent to uncore.",
337 "EventCode": "0xB0",
338 "Counter": "0,1,2,3",
339 "UMask": "0x2",
340 "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
341 "SampleAfterValue": "100003",
342 "BriefDescription": "Cacheable and noncachaeble code read requests",
343 "CounterHTOff": "0,1,2,3,4,5,6,7"
344 },
345 {
346 "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.",
347 "EventCode": "0xB0",
348 "Counter": "0,1,2,3",
349 "UMask": "0x4",
350 "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
351 "SampleAfterValue": "100003",
352 "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
353 "CounterHTOff": "0,1,2,3,4,5,6,7"
354 },
355 {
356 "PublicDescription": "Data read requests sent to uncore (demand and prefetch).",
357 "EventCode": "0xB0",
358 "Counter": "0,1,2,3",
359 "UMask": "0x8",
360 "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
361 "SampleAfterValue": "100003",
362 "BriefDescription": "Demand and prefetch data reads",
363 "CounterHTOff": "0,1,2,3,4,5,6,7"
364 },
365 {
366 "PublicDescription": "Cases when offcore requests buffer cannot take more entries for core.",
367 "EventCode": "0xB2",
368 "Counter": "0,1,2,3",
369 "UMask": "0x1",
370 "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
371 "SampleAfterValue": "2000003",
372 "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core",
373 "CounterHTOff": "0,1,2,3,4,5,6,7"
374 },
375 {
376 "PEBS": "1",
377 "EventCode": "0xD0",
378 "Counter": "0,1,2,3",
379 "UMask": "0x11",
380 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
381 "SampleAfterValue": "100003",
382 "BriefDescription": "Retired load uops that miss the STLB.",
383 "CounterHTOff": "0,1,2,3"
384 },
385 {
386 "PEBS": "1",
387 "EventCode": "0xD0",
388 "Counter": "0,1,2,3",
389 "UMask": "0x12",
390 "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
391 "SampleAfterValue": "100003",
392 "BriefDescription": "Retired store uops that miss the STLB.",
393 "CounterHTOff": "0,1,2,3"
394 },
395 {
396 "PEBS": "1",
397 "EventCode": "0xD0",
398 "Counter": "0,1,2,3",
399 "UMask": "0x21",
400 "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
401 "SampleAfterValue": "100007",
402 "BriefDescription": "Retired load uops with locked access.",
403 "CounterHTOff": "0,1,2,3"
404 },
405 {
406 "PEBS": "1",
407 "EventCode": "0xD0",
408 "Counter": "0,1,2,3",
409 "UMask": "0x41",
410 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
411 "SampleAfterValue": "100003",
412 "BriefDescription": "Retired load uops that split across a cacheline boundary.",
413 "CounterHTOff": "0,1,2,3"
414 },
415 {
416 "PEBS": "1",
417 "EventCode": "0xD0",
418 "Counter": "0,1,2,3",
419 "UMask": "0x42",
420 "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
421 "SampleAfterValue": "100003",
422 "BriefDescription": "Retired store uops that split across a cacheline boundary.",
423 "CounterHTOff": "0,1,2,3"
424 },
425 {
426 "PEBS": "1",
427 "EventCode": "0xD0",
428 "Counter": "0,1,2,3",
429 "UMask": "0x81",
430 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
431 "SampleAfterValue": "2000003",
432 "BriefDescription": "All retired load uops.",
433 "CounterHTOff": "0,1,2,3"
434 },
435 {
436 "PEBS": "1",
437 "EventCode": "0xD0",
438 "Counter": "0,1,2,3",
439 "UMask": "0x82",
440 "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
441 "SampleAfterValue": "2000003",
442 "BriefDescription": "All retired store uops.",
443 "CounterHTOff": "0,1,2,3"
444 },
445 {
446 "PEBS": "1",
447 "PublicDescription": "Retired load uops with L1 cache hits as data sources.",
448 "EventCode": "0xD1",
449 "Counter": "0,1,2,3",
450 "UMask": "0x1",
451 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
452 "SampleAfterValue": "2000003",
453 "BriefDescription": "Retired load uops with L1 cache hits as data sources. ",
454 "CounterHTOff": "0,1,2,3"
455 },
456 {
457 "PEBS": "1",
458 "PublicDescription": "Retired load uops with L2 cache hits as data sources.",
459 "EventCode": "0xD1",
460 "Counter": "0,1,2,3",
461 "UMask": "0x2",
462 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
463 "SampleAfterValue": "100003",
464 "BriefDescription": "Retired load uops with L2 cache hits as data sources. ",
465 "CounterHTOff": "0,1,2,3"
466 },
467 {
468 "PEBS": "1",
469 "PublicDescription": "Retired load uops whose data source was LLC hit with no snoop required.",
470 "EventCode": "0xD1",
471 "Counter": "0,1,2,3",
472 "UMask": "0x4",
473 "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT",
474 "SampleAfterValue": "50021",
475 "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required. ",
476 "CounterHTOff": "0,1,2,3"
477 },
478 {
479 "PEBS": "1",
480 "PublicDescription": "Retired load uops whose data source followed an L1 miss.",
481 "EventCode": "0xD1",
482 "Counter": "0,1,2,3",
483 "UMask": "0x8",
484 "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
485 "SampleAfterValue": "100003",
486 "BriefDescription": "Retired load uops which data sources following L1 data-cache miss",
487 "CounterHTOff": "0,1,2,3"
488 },
489 {
490 "PEBS": "1",
491 "PublicDescription": "Retired load uops that missed L2, excluding unknown sources.",
492 "EventCode": "0xD1",
493 "Counter": "0,1,2,3",
494 "UMask": "0x10",
495 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
496 "SampleAfterValue": "50021",
497 "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknown data-source.",
498 "CounterHTOff": "0,1,2,3"
499 },
500 {
501 "PEBS": "1",
502 "PublicDescription": "Retired load uops whose data source is LLC miss.",
503 "EventCode": "0xD1",
504 "Counter": "0,1,2,3",
505 "UMask": "0x20",
506 "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS",
507 "SampleAfterValue": "100007",
508 "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
509 "CounterHTOff": "0,1,2,3"
510 },
511 {
512 "PEBS": "1",
513 "PublicDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
514 "EventCode": "0xD1",
515 "Counter": "0,1,2,3",
516 "UMask": "0x40",
517 "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
518 "SampleAfterValue": "100003",
519 "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. ",
520 "CounterHTOff": "0,1,2,3"
521 },
522 {
523 "PEBS": "1",
524 "PublicDescription": "Retired load uops whose data source was an on-package core cache LLC hit and cross-core snoop missed.",
525 "EventCode": "0xD2",
526 "Counter": "0,1,2,3",
527 "UMask": "0x1",
528 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS",
529 "SampleAfterValue": "20011",
530 "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. ",
531 "CounterHTOff": "0,1,2,3"
532 },
533 {
534 "PEBS": "1",
535 "PublicDescription": "Retired load uops whose data source was an on-package LLC hit and cross-core snoop hits.",
536 "EventCode": "0xD2",
537 "Counter": "0,1,2,3",
538 "UMask": "0x2",
539 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT",
540 "SampleAfterValue": "20011",
541 "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. ",
542 "CounterHTOff": "0,1,2,3"
543 },
544 {
545 "PEBS": "1",
546 "PublicDescription": "Retired load uops whose data source was an on-package core cache with HitM responses.",
547 "EventCode": "0xD2",
548 "Counter": "0,1,2,3",
549 "UMask": "0x4",
550 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM",
551 "SampleAfterValue": "20011",
552 "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC. ",
553 "CounterHTOff": "0,1,2,3"
554 },
555 {
556 "PEBS": "1",
557 "PublicDescription": "Retired load uops whose data source was LLC hit with no snoop required.",
558 "EventCode": "0xD2",
559 "Counter": "0,1,2,3",
560 "UMask": "0x8",
561 "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE",
562 "SampleAfterValue": "100003",
563 "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required. ",
564 "CounterHTOff": "0,1,2,3"
565 },
566 {
567 "PublicDescription": "Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI)",
568 "EventCode": "0xD3",
569 "Counter": "0,1,2,3",
570 "UMask": "0x1",
571 "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM",
572 "SampleAfterValue": "100007",
573 "BriefDescription": "Retired load uops which data sources missed LLC but serviced from local dram.",
574 "CounterHTOff": "0,1,2,3"
575 },
576 {
577 "EventCode": "0xD3",
578 "Counter": "0,1,2,3",
579 "UMask": "0xc",
580 "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM",
581 "SampleAfterValue": "100007",
582 "BriefDescription": "Retired load uops whose data source was remote DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).",
583 "CounterHTOff": "0,1,2,3"
584 },
585 {
586 "EventCode": "0xD3",
587 "Counter": "0,1,2,3",
588 "UMask": "0x10",
589 "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM",
590 "SampleAfterValue": "100007",
591 "BriefDescription": "Remote cache HITM.",
592 "CounterHTOff": "0,1,2,3"
593 },
594 {
595 "EventCode": "0xD3",
596 "Counter": "0,1,2,3",
597 "UMask": "0x20",
598 "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD",
599 "SampleAfterValue": "100007",
600 "BriefDescription": "Data forwarded from remote cache.",
601 "CounterHTOff": "0,1,2,3"
602 },
603 {
604 "PublicDescription": "Demand Data Read requests that access L2 cache.",
605 "EventCode": "0xF0",
606 "Counter": "0,1,2,3",
607 "UMask": "0x1",
608 "EventName": "L2_TRANS.DEMAND_DATA_RD",
609 "SampleAfterValue": "200003",
610 "BriefDescription": "Demand Data Read requests that access L2 cache",
611 "CounterHTOff": "0,1,2,3,4,5,6,7"
612 },
613 {
614 "PublicDescription": "RFO requests that access L2 cache.",
615 "EventCode": "0xF0",
616 "Counter": "0,1,2,3",
617 "UMask": "0x2",
618 "EventName": "L2_TRANS.RFO",
619 "SampleAfterValue": "200003",
620 "BriefDescription": "RFO requests that access L2 cache",
621 "CounterHTOff": "0,1,2,3,4,5,6,7"
622 },
623 {
624 "PublicDescription": "L2 cache accesses when fetching instructions.",
625 "EventCode": "0xF0",
626 "Counter": "0,1,2,3",
627 "UMask": "0x4",
628 "EventName": "L2_TRANS.CODE_RD",
629 "SampleAfterValue": "200003",
630 "BriefDescription": "L2 cache accesses when fetching instructions",
631 "CounterHTOff": "0,1,2,3,4,5,6,7"
632 },
633 {
634 "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.",
635 "EventCode": "0xF0",
636 "Counter": "0,1,2,3",
637 "UMask": "0x8",
638 "EventName": "L2_TRANS.ALL_PF",
639 "SampleAfterValue": "200003",
640 "BriefDescription": "L2 or LLC HW prefetches that access L2 cache",
641 "CounterHTOff": "0,1,2,3,4,5,6,7"
642 },
643 {
644 "PublicDescription": "L1D writebacks that access L2 cache.",
645 "EventCode": "0xF0",
646 "Counter": "0,1,2,3",
647 "UMask": "0x10",
648 "EventName": "L2_TRANS.L1D_WB",
649 "SampleAfterValue": "200003",
650 "BriefDescription": "L1D writebacks that access L2 cache",
651 "CounterHTOff": "0,1,2,3,4,5,6,7"
652 },
653 {
654 "PublicDescription": "L2 fill requests that access L2 cache.",
655 "EventCode": "0xF0",
656 "Counter": "0,1,2,3",
657 "UMask": "0x20",
658 "EventName": "L2_TRANS.L2_FILL",
659 "SampleAfterValue": "200003",
660 "BriefDescription": "L2 fill requests that access L2 cache",
661 "CounterHTOff": "0,1,2,3,4,5,6,7"
662 },
663 {
664 "PublicDescription": "L2 writebacks that access L2 cache.",
665 "EventCode": "0xF0",
666 "Counter": "0,1,2,3",
667 "UMask": "0x40",
668 "EventName": "L2_TRANS.L2_WB",
669 "SampleAfterValue": "200003",
670 "BriefDescription": "L2 writebacks that access L2 cache",
671 "CounterHTOff": "0,1,2,3,4,5,6,7"
672 },
673 {
674 "PublicDescription": "Transactions accessing L2 pipe.",
675 "EventCode": "0xF0",
676 "Counter": "0,1,2,3",
677 "UMask": "0x80",
678 "EventName": "L2_TRANS.ALL_REQUESTS",
679 "SampleAfterValue": "200003",
680 "BriefDescription": "Transactions accessing L2 pipe",
681 "CounterHTOff": "0,1,2,3,4,5,6,7"
682 },
683 {
684 "PublicDescription": "L2 cache lines in I state filling L2.",
685 "EventCode": "0xF1",
686 "Counter": "0,1,2,3",
687 "UMask": "0x1",
688 "EventName": "L2_LINES_IN.I",
689 "SampleAfterValue": "100003",
690 "BriefDescription": "L2 cache lines in I state filling L2",
691 "CounterHTOff": "0,1,2,3,4,5,6,7"
692 },
693 {
694 "PublicDescription": "L2 cache lines in S state filling L2.",
695 "EventCode": "0xF1",
696 "Counter": "0,1,2,3",
697 "UMask": "0x2",
698 "EventName": "L2_LINES_IN.S",
699 "SampleAfterValue": "100003",
700 "BriefDescription": "L2 cache lines in S state filling L2",
701 "CounterHTOff": "0,1,2,3,4,5,6,7"
702 },
703 {
704 "PublicDescription": "L2 cache lines in E state filling L2.",
705 "EventCode": "0xF1",
706 "Counter": "0,1,2,3",
707 "UMask": "0x4",
708 "EventName": "L2_LINES_IN.E",
709 "SampleAfterValue": "100003",
710 "BriefDescription": "L2 cache lines in E state filling L2",
711 "CounterHTOff": "0,1,2,3,4,5,6,7"
712 },
713 {
714 "PublicDescription": "L2 cache lines filling L2.",
715 "EventCode": "0xF1",
716 "Counter": "0,1,2,3",
717 "UMask": "0x7",
718 "EventName": "L2_LINES_IN.ALL",
719 "SampleAfterValue": "100003",
720 "BriefDescription": "L2 cache lines filling L2",
721 "CounterHTOff": "0,1,2,3,4,5,6,7"
722 },
723 {
724 "PublicDescription": "Clean L2 cache lines evicted by demand.",
725 "EventCode": "0xF2",
726 "Counter": "0,1,2,3",
727 "UMask": "0x1",
728 "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
729 "SampleAfterValue": "100003",
730 "BriefDescription": "Clean L2 cache lines evicted by demand",
731 "CounterHTOff": "0,1,2,3,4,5,6,7"
732 },
733 {
734 "PublicDescription": "Dirty L2 cache lines evicted by demand.",
735 "EventCode": "0xF2",
736 "Counter": "0,1,2,3",
737 "UMask": "0x2",
738 "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
739 "SampleAfterValue": "100003",
740 "BriefDescription": "Dirty L2 cache lines evicted by demand",
741 "CounterHTOff": "0,1,2,3,4,5,6,7"
742 },
743 {
744 "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.",
745 "EventCode": "0xF2",
746 "Counter": "0,1,2,3",
747 "UMask": "0x4",
748 "EventName": "L2_LINES_OUT.PF_CLEAN",
749 "SampleAfterValue": "100003",
750 "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch",
751 "CounterHTOff": "0,1,2,3,4,5,6,7"
752 },
753 {
754 "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.",
755 "EventCode": "0xF2",
756 "Counter": "0,1,2,3",
757 "UMask": "0x8",
758 "EventName": "L2_LINES_OUT.PF_DIRTY",
759 "SampleAfterValue": "100003",
760 "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch",
761 "CounterHTOff": "0,1,2,3,4,5,6,7"
762 },
763 {
764 "PublicDescription": "Dirty L2 cache lines filling the L2.",
765 "EventCode": "0xF2",
766 "Counter": "0,1,2,3",
767 "UMask": "0xa",
768 "EventName": "L2_LINES_OUT.DIRTY_ALL",
769 "SampleAfterValue": "100003",
770 "BriefDescription": "Dirty L2 cache lines filling the L2",
771 "CounterHTOff": "0,1,2,3,4,5,6,7"
772 },
773 {
774 "EventCode": "0xF4",
775 "Counter": "0,1,2,3",
776 "UMask": "0x10",
777 "EventName": "SQ_MISC.SPLIT_LOCK",
778 "SampleAfterValue": "100003",
779 "BriefDescription": "Split locks in SQ",
780 "CounterHTOff": "0,1,2,3,4,5,6,7"
781 },
782 {
783 "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
784 "EventCode": "0x60",
785 "Counter": "0,1,2,3",
786 "UMask": "0x1",
787 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
788 "SampleAfterValue": "2000003",
789 "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue",
790 "CounterMask": "6",
791 "CounterHTOff": "0,1,2,3,4,5,6,7"
792 },
793 {
794 "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
795 "EventCode": "0x48",
796 "Counter": "2",
797 "UMask": "0x1",
798 "AnyThread": "1",
799 "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
800 "SampleAfterValue": "2000003",
801 "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core",
802 "CounterMask": "1",
803 "CounterHTOff": "2"
804 },
805 {
806 "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
807 "EventCode": "0x48",
808 "Counter": "0,1,2,3",
809 "UMask": "0x2",
810 "EventName": "L1D_PEND_MISS.FB_FULL",
811 "SampleAfterValue": "2000003",
812 "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability",
813 "CounterMask": "1",
814 "CounterHTOff": "0,1,2,3,4,5,6,7"
815 },
816 {
817 "EventCode": "0xB7, 0xBB",
818 "MSRValue": "0x4003c0091",
819 "Counter": "0,1,2,3",
820 "UMask": "0x1",
821 "Offcore": "1",
822 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
823 "MSRIndex": "0x1a6,0x1a7",
824 "SampleAfterValue": "100003",
825 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
826 "CounterHTOff": "0,1,2,3"
827 },
828 {
829 "EventCode": "0xB7, 0xBB",
830 "MSRValue": "0x10003c0091",
831 "Counter": "0,1,2,3",
832 "UMask": "0x1",
833 "Offcore": "1",
834 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
835 "MSRIndex": "0x1a6,0x1a7",
836 "SampleAfterValue": "100003",
837 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
838 "CounterHTOff": "0,1,2,3"
839 },
840 {
841 "EventCode": "0xB7, 0xBB",
842 "MSRValue": "0x1003c0091",
843 "Counter": "0,1,2,3",
844 "UMask": "0x1",
845 "Offcore": "1",
846 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
847 "MSRIndex": "0x1a6,0x1a7",
848 "SampleAfterValue": "100003",
849 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
850 "CounterHTOff": "0,1,2,3"
851 },
852 {
853 "EventCode": "0xB7, 0xBB",
854 "MSRValue": "0x2003c0091",
855 "Counter": "0,1,2,3",
856 "UMask": "0x1",
857 "Offcore": "1",
858 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS",
859 "MSRIndex": "0x1a6,0x1a7",
860 "SampleAfterValue": "100003",
861 "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",
862 "CounterHTOff": "0,1,2,3"
863 },
864 {
865 "EventCode": "0xB7, 0xBB",
866 "MSRValue": "0x3f803c0090",
867 "Counter": "0,1,2,3",
868 "UMask": "0x1",
869 "Offcore": "1",
870 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE",
871 "MSRIndex": "0x1a6,0x1a7",
872 "SampleAfterValue": "100003",
873 "BriefDescription": "Counts all prefetch data reads that hit the LLC",
874 "CounterHTOff": "0,1,2,3"
875 },
876 {
877 "EventCode": "0xB7, 0xBB",
878 "MSRValue": "0x4003c0090",
879 "Counter": "0,1,2,3",
880 "UMask": "0x1",
881 "Offcore": "1",
882 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
883 "MSRIndex": "0x1a6,0x1a7",
884 "SampleAfterValue": "100003",
885 "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
886 "CounterHTOff": "0,1,2,3"
887 },
888 {
889 "EventCode": "0xB7, 0xBB",
890 "MSRValue": "0x10003c0090",
891 "Counter": "0,1,2,3",
892 "UMask": "0x1",
893 "Offcore": "1",
894 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
895 "MSRIndex": "0x1a6,0x1a7",
896 "SampleAfterValue": "100003",
897 "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
898 "CounterHTOff": "0,1,2,3"
899 },
900 {
901 "EventCode": "0xB7, 0xBB",
902 "MSRValue": "0x1003c0090",
903 "Counter": "0,1,2,3",
904 "UMask": "0x1",
905 "Offcore": "1",
906 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
907 "MSRIndex": "0x1a6,0x1a7",
908 "SampleAfterValue": "100003",
909 "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
910 "CounterHTOff": "0,1,2,3"
911 },
912 {
913 "EventCode": "0xB7, 0xBB",
914 "MSRValue": "0x2003c0090",
915 "Counter": "0,1,2,3",
916 "UMask": "0x1",
917 "Offcore": "1",
918 "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS",
919 "MSRIndex": "0x1a6,0x1a7",
920 "SampleAfterValue": "100003",
921 "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",
922 "CounterHTOff": "0,1,2,3"
923 },
924 {
925 "EventCode": "0xB7, 0xBB",
926 "MSRValue": "0x3f803c03f7",
927 "Counter": "0,1,2,3",
928 "UMask": "0x1",
929 "Offcore": "1",
930 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE",
931 "MSRIndex": "0x1a6,0x1a7",
932 "SampleAfterValue": "100003",
933 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC",
934 "CounterHTOff": "0,1,2,3"
935 },
936 {
937 "EventCode": "0xB7, 0xBB",
938 "MSRValue": "0x4003c03f7",
939 "Counter": "0,1,2,3",
940 "UMask": "0x1",
941 "Offcore": "1",
942 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
943 "MSRIndex": "0x1a6,0x1a7",
944 "SampleAfterValue": "100003",
945 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
946 "CounterHTOff": "0,1,2,3"
947 },
948 {
949 "EventCode": "0xB7, 0xBB",
950 "MSRValue": "0x10003c03f7",
951 "Counter": "0,1,2,3",
952 "UMask": "0x1",
953 "Offcore": "1",
954 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",
955 "MSRIndex": "0x1a6,0x1a7",
956 "SampleAfterValue": "100003",
957 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
958 "CounterHTOff": "0,1,2,3"
959 },
960 {
961 "EventCode": "0xB7, 0xBB",
962 "MSRValue": "0x1003c03f7",
963 "Counter": "0,1,2,3",
964 "UMask": "0x1",
965 "Offcore": "1",
966 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED",
967 "MSRIndex": "0x1a6,0x1a7",
968 "SampleAfterValue": "100003",
969 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
970 "CounterHTOff": "0,1,2,3"
971 },
972 {
973 "EventCode": "0xB7, 0xBB",
974 "MSRValue": "0x2003c03f7",
975 "Counter": "0,1,2,3",
976 "UMask": "0x1",
977 "Offcore": "1",
978 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS",
979 "MSRIndex": "0x1a6,0x1a7",
980 "SampleAfterValue": "100003",
981 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response",
982 "CounterHTOff": "0,1,2,3"
983 },
984 {
985 "EventCode": "0xB7, 0xBB",
986 "MSRValue": "0x10008",
987 "Counter": "0,1,2,3",
988 "UMask": "0x1",
989 "Offcore": "1",
990 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
991 "MSRIndex": "0x1a6,0x1a7",
992 "SampleAfterValue": "100003",
993 "BriefDescription": "Counts all writebacks from the core to the LLC",
994 "CounterHTOff": "0,1,2,3"
995 },
996 {
997 "EventCode": "0xB7, 0xBB",
998 "MSRValue": "0x3f803c0004",
999 "Counter": "0,1,2,3",
1000 "UMask": "0x1",
1001 "Offcore": "1",
1002 "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",
1003 "MSRIndex": "0x1a6,0x1a7",
1004 "SampleAfterValue": "100003",
1005 "BriefDescription": "Counts all demand code reads that hit in the LLC",
1006 "CounterHTOff": "0,1,2,3"
1007 },
1008 {
1009 "EventCode": "0xB7, 0xBB",
1010 "MSRValue": "0x3f803c0001",
1011 "Counter": "0,1,2,3",
1012 "UMask": "0x1",
1013 "Offcore": "1",
1014 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",
1015 "MSRIndex": "0x1a6,0x1a7",
1016 "SampleAfterValue": "100003",
1017 "BriefDescription": "Counts all demand data reads that hit in the LLC",
1018 "CounterHTOff": "0,1,2,3"
1019 },
1020 {
1021 "EventCode": "0xB7, 0xBB",
1022 "MSRValue": "0x4003c0001",
1023 "Counter": "0,1,2,3",
1024 "UMask": "0x1",
1025 "Offcore": "1",
1026 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1027 "MSRIndex": "0x1a6,0x1a7",
1028 "SampleAfterValue": "100003",
1029 "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1030 "CounterHTOff": "0,1,2,3"
1031 },
1032 {
1033 "EventCode": "0xB7, 0xBB",
1034 "MSRValue": "0x10003c0001",
1035 "Counter": "0,1,2,3",
1036 "UMask": "0x1",
1037 "Offcore": "1",
1038 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
1039 "MSRIndex": "0x1a6,0x1a7",
1040 "SampleAfterValue": "100003",
1041 "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1042 "CounterHTOff": "0,1,2,3"
1043 },
1044 {
1045 "EventCode": "0xB7, 0xBB",
1046 "MSRValue": "0x1003c0001",
1047 "Counter": "0,1,2,3",
1048 "UMask": "0x1",
1049 "Offcore": "1",
1050 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
1051 "MSRIndex": "0x1a6,0x1a7",
1052 "SampleAfterValue": "100003",
1053 "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
1054 "CounterHTOff": "0,1,2,3"
1055 },
1056 {
1057 "EventCode": "0xB7, 0xBB",
1058 "MSRValue": "0x2003c0001",
1059 "Counter": "0,1,2,3",
1060 "UMask": "0x1",
1061 "Offcore": "1",
1062 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS",
1063 "MSRIndex": "0x1a6,0x1a7",
1064 "SampleAfterValue": "100003",
1065 "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response",
1066 "CounterHTOff": "0,1,2,3"
1067 },
1068 {
1069 "EventCode": "0xB7, 0xBB",
1070 "MSRValue": "0x10003c0002",
1071 "Counter": "0,1,2,3",
1072 "UMask": "0x1",
1073 "Offcore": "1",
1074 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
1075 "MSRIndex": "0x1a6,0x1a7",
1076 "SampleAfterValue": "100003",
1077 "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1078 "CounterHTOff": "0,1,2,3"
1079 },
1080 {
1081 "EventCode": "0xB7, 0xBB",
1082 "MSRValue": "0x803c8000",
1083 "Counter": "0,1,2,3",
1084 "UMask": "0x1",
1085 "Offcore": "1",
1086 "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS",
1087 "MSRIndex": "0x1a6,0x1a7",
1088 "SampleAfterValue": "100003",
1089 "BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches",
1090 "CounterHTOff": "0,1,2,3"
1091 },
1092 {
1093 "EventCode": "0xB7, 0xBB",
1094 "MSRValue": "0x23ffc08000",
1095 "Counter": "0,1,2,3",
1096 "UMask": "0x1",
1097 "Offcore": "1",
1098 "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC",
1099 "MSRIndex": "0x1a6,0x1a7",
1100 "SampleAfterValue": "100003",
1101 "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses",
1102 "CounterHTOff": "0,1,2,3"
1103 },
1104 {
1105 "EventCode": "0xB7, 0xBB",
1106 "MSRValue": "0x3f803c0040",
1107 "Counter": "0,1,2,3",
1108 "UMask": "0x1",
1109 "Offcore": "1",
1110 "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",
1111 "MSRIndex": "0x1a6,0x1a7",
1112 "SampleAfterValue": "100003",
1113 "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC",
1114 "CounterHTOff": "0,1,2,3"
1115 },
1116 {
1117 "EventCode": "0xB7, 0xBB",
1118 "MSRValue": "0x3f803c0010",
1119 "Counter": "0,1,2,3",
1120 "UMask": "0x1",
1121 "Offcore": "1",
1122 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",
1123 "MSRIndex": "0x1a6,0x1a7",
1124 "SampleAfterValue": "100003",
1125 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC",
1126 "CounterHTOff": "0,1,2,3"
1127 },
1128 {
1129 "EventCode": "0xB7, 0xBB",
1130 "MSRValue": "0x4003c0010",
1131 "Counter": "0,1,2,3",
1132 "UMask": "0x1",
1133 "Offcore": "1",
1134 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1135 "MSRIndex": "0x1a6,0x1a7",
1136 "SampleAfterValue": "100003",
1137 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1138 "CounterHTOff": "0,1,2,3"
1139 },
1140 {
1141 "EventCode": "0xB7, 0xBB",
1142 "MSRValue": "0x10003c0010",
1143 "Counter": "0,1,2,3",
1144 "UMask": "0x1",
1145 "Offcore": "1",
1146 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
1147 "MSRIndex": "0x1a6,0x1a7",
1148 "SampleAfterValue": "100003",
1149 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1150 "CounterHTOff": "0,1,2,3"
1151 },
1152 {
1153 "EventCode": "0xB7, 0xBB",
1154 "MSRValue": "0x1003c0010",
1155 "Counter": "0,1,2,3",
1156 "UMask": "0x1",
1157 "Offcore": "1",
1158 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
1159 "MSRIndex": "0x1a6,0x1a7",
1160 "SampleAfterValue": "100003",
1161 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
1162 "CounterHTOff": "0,1,2,3"
1163 },
1164 {
1165 "EventCode": "0xB7, 0xBB",
1166 "MSRValue": "0x2003c0010",
1167 "Counter": "0,1,2,3",
1168 "UMask": "0x1",
1169 "Offcore": "1",
1170 "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS",
1171 "MSRIndex": "0x1a6,0x1a7",
1172 "SampleAfterValue": "100003",
1173 "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
1174 "CounterHTOff": "0,1,2,3"
1175 },
1176 {
1177 "EventCode": "0xB7, 0xBB",
1178 "MSRValue": "0x3f803c0200",
1179 "Counter": "0,1,2,3",
1180 "UMask": "0x1",
1181 "Offcore": "1",
1182 "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",
1183 "MSRIndex": "0x1a6,0x1a7",
1184 "SampleAfterValue": "100003",
1185 "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC",
1186 "CounterHTOff": "0,1,2,3"
1187 },
1188 {
1189 "EventCode": "0xB7, 0xBB",
1190 "MSRValue": "0x3f803c0080",
1191 "Counter": "0,1,2,3",
1192 "UMask": "0x1",
1193 "Offcore": "1",
1194 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",
1195 "MSRIndex": "0x1a6,0x1a7",
1196 "SampleAfterValue": "100003",
1197 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC",
1198 "CounterHTOff": "0,1,2,3"
1199 },
1200 {
1201 "EventCode": "0xB7, 0xBB",
1202 "MSRValue": "0x4003c0080",
1203 "Counter": "0,1,2,3",
1204 "UMask": "0x1",
1205 "Offcore": "1",
1206 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
1207 "MSRIndex": "0x1a6,0x1a7",
1208 "SampleAfterValue": "100003",
1209 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
1210 "CounterHTOff": "0,1,2,3"
1211 },
1212 {
1213 "EventCode": "0xB7, 0xBB",
1214 "MSRValue": "0x10003c0080",
1215 "Counter": "0,1,2,3",
1216 "UMask": "0x1",
1217 "Offcore": "1",
1218 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
1219 "MSRIndex": "0x1a6,0x1a7",
1220 "SampleAfterValue": "100003",
1221 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
1222 "CounterHTOff": "0,1,2,3"
1223 },
1224 {
1225 "EventCode": "0xB7, 0xBB",
1226 "MSRValue": "0x1003c0080",
1227 "Counter": "0,1,2,3",
1228 "UMask": "0x1",
1229 "Offcore": "1",
1230 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
1231 "MSRIndex": "0x1a6,0x1a7",
1232 "SampleAfterValue": "100003",
1233 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
1234 "CounterHTOff": "0,1,2,3"
1235 },
1236 {
1237 "EventCode": "0xB7, 0xBB",
1238 "MSRValue": "0x2003c0080",
1239 "Counter": "0,1,2,3",
1240 "UMask": "0x1",
1241 "Offcore": "1",
1242 "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS",
1243 "MSRIndex": "0x1a6,0x1a7",
1244 "SampleAfterValue": "100003",
1245 "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
1246 "CounterHTOff": "0,1,2,3"
1247 },
1248 {
1249 "EventCode": "0xB7, 0xBB",
1250 "MSRValue": "0x10400",
1251 "Counter": "0,1,2,3",
1252 "UMask": "0x1",
1253 "Offcore": "1",
1254 "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",
1255 "MSRIndex": "0x1a6,0x1a7",
1256 "SampleAfterValue": "100003",
1257 "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address",
1258 "CounterHTOff": "0,1,2,3"
1259 },
1260 {
1261 "EventCode": "0xB7, 0xBB",
1262 "MSRValue": "0x10800",
1263 "Counter": "0,1,2,3",
1264 "UMask": "0x1",
1265 "Offcore": "1",
1266 "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
1267 "MSRIndex": "0x1a6,0x1a7",
1268 "SampleAfterValue": "100003",
1269 "BriefDescription": "Counts non-temporal stores",
1270 "CounterHTOff": "0,1,2,3"
1271 }
1272 ]