| blob | 8812b70f39111d0d777ae6c4ae1a90f297678d2f |
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
4 */
6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/px30-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
14 / {
15 compatible = "rockchip,px30";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
21 aliases {
22 ethernet0 = &gmac;
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 serial0 = &uart0;
28 serial1 = &uart1;
29 serial2 = &uart2;
30 serial3 = &uart3;
31 serial4 = &uart4;
32 serial5 = &uart5;
33 spi0 = &spi0;
34 spi1 = &spi1;
35 };
37 cpus {
38 #address-cells = <2>;
39 #size-cells = <0>;
41 cpu0: cpu@0 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a35";
44 reg = <0x0 0x0>;
45 enable-method = "psci";
46 clocks = <&cru ARMCLK>;
47 #cooling-cells = <2>;
48 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
49 dynamic-power-coefficient = <90>;
50 operating-points-v2 = <&cpu0_opp_table>;
51 };
53 cpu1: cpu@1 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a35";
56 reg = <0x0 0x1>;
57 enable-method = "psci";
58 clocks = <&cru ARMCLK>;
59 #cooling-cells = <2>;
60 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
61 dynamic-power-coefficient = <90>;
62 operating-points-v2 = <&cpu0_opp_table>;
63 };
65 cpu2: cpu@2 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a35";
68 reg = <0x0 0x2>;
69 enable-method = "psci";
70 clocks = <&cru ARMCLK>;
71 #cooling-cells = <2>;
72 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
73 dynamic-power-coefficient = <90>;
74 operating-points-v2 = <&cpu0_opp_table>;
75 };
77 cpu3: cpu@3 {
78 device_type = "cpu";
79 compatible = "arm,cortex-a35";
80 reg = <0x0 0x3>;
81 enable-method = "psci";
82 clocks = <&cru ARMCLK>;
83 #cooling-cells = <2>;
84 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
85 dynamic-power-coefficient = <90>;
86 operating-points-v2 = <&cpu0_opp_table>;
87 };
89 idle-states {
90 entry-method = "psci";
92 CPU_SLEEP: cpu-sleep {
93 compatible = "arm,idle-state";
94 local-timer-stop;
95 arm,psci-suspend-param = <0x0010000>;
96 entry-latency-us = <120>;
97 exit-latency-us = <250>;
98 min-residency-us = <900>;
99 };
101 CLUSTER_SLEEP: cluster-sleep {
102 compatible = "arm,idle-state";
103 local-timer-stop;
104 arm,psci-suspend-param = <0x1010000>;
105 entry-latency-us = <400>;
106 exit-latency-us = <500>;
107 min-residency-us = <2000>;
108 };
109 };
110 };
112 cpu0_opp_table: cpu0-opp-table {
113 compatible = "operating-points-v2";
114 opp-shared;
116 opp-408000000 {
117 opp-hz = /bits/ 64 <408000000>;
118 opp-microvolt = <950000 950000 1350000>;
119 clock-latency-ns = <40000>;
120 opp-suspend;
121 };
122 opp-600000000 {
123 opp-hz = /bits/ 64 <600000000>;
124 opp-microvolt = <950000 950000 1350000>;
125 clock-latency-ns = <40000>;
126 };
127 opp-816000000 {
128 opp-hz = /bits/ 64 <816000000>;
129 opp-microvolt = <1050000 1050000 1350000>;
130 clock-latency-ns = <40000>;
131 };
132 opp-1008000000 {
133 opp-hz = /bits/ 64 <1008000000>;
134 opp-microvolt = <1175000 1175000 1350000>;
135 clock-latency-ns = <40000>;
136 };
137 opp-1200000000 {
138 opp-hz = /bits/ 64 <1200000000>;
139 opp-microvolt = <1300000 1300000 1350000>;
140 clock-latency-ns = <40000>;
141 };
142 opp-1296000000 {
143 opp-hz = /bits/ 64 <1296000000>;
144 opp-microvolt = <1350000 1350000 1350000>;
145 clock-latency-ns = <40000>;
146 };
147 };
149 arm-pmu {
150 compatible = "arm,cortex-a53-pmu";
151 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
155 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
156 };
158 display_subsystem: display-subsystem {
159 compatible = "rockchip,display-subsystem";
160 ports = <&vopb_out>, <&vopl_out>;
161 status = "disabled";
162 };
164 gmac_clkin: external-gmac-clock {
165 compatible = "fixed-clock";
166 clock-frequency = <50000000>;
167 clock-output-names = "gmac_clkin";
168 #clock-cells = <0>;
169 };
171 psci {
172 compatible = "arm,psci-1.0";
173 method = "smc";
174 };
176 timer {
177 compatible = "arm,armv8-timer";
178 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
179 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
180 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
181 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
182 };
184 xin24m: xin24m {
185 compatible = "fixed-clock";
186 #clock-cells = <0>;
187 clock-frequency = <24000000>;
188 clock-output-names = "xin24m";
189 };
191 pmu: power-management@ff000000 {
192 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
193 reg = <0x0 0xff000000 0x0 0x1000>;
195 power: power-controller {
196 compatible = "rockchip,px30-power-controller";
197 #power-domain-cells = <1>;
198 #address-cells = <1>;
199 #size-cells = <0>;
201 /* These power domains are grouped by VD_LOGIC */
202 pd_usb@PX30_PD_USB {
203 reg = <PX30_PD_USB>;
204 clocks = <&cru HCLK_HOST>,
205 <&cru HCLK_OTG>,
206 <&cru SCLK_OTG_ADP>;
207 pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
208 };
209 pd_sdcard@PX30_PD_SDCARD {
210 reg = <PX30_PD_SDCARD>;
211 clocks = <&cru HCLK_SDMMC>,
212 <&cru SCLK_SDMMC>;
213 pm_qos = <&qos_sdmmc>;
214 };
215 pd_gmac@PX30_PD_GMAC {
216 reg = <PX30_PD_GMAC>;
217 clocks = <&cru ACLK_GMAC>,
218 <&cru PCLK_GMAC>,
219 <&cru SCLK_MAC_REF>,
220 <&cru SCLK_GMAC_RX_TX>;
221 pm_qos = <&qos_gmac>;
222 };
223 pd_mmc_nand@PX30_PD_MMC_NAND {
224 reg = <PX30_PD_MMC_NAND>;
225 clocks = <&cru HCLK_NANDC>,
226 <&cru HCLK_EMMC>,
227 <&cru HCLK_SDIO>,
228 <&cru HCLK_SFC>,
229 <&cru SCLK_EMMC>,
230 <&cru SCLK_NANDC>,
231 <&cru SCLK_SDIO>,
232 <&cru SCLK_SFC>;
233 pm_qos = <&qos_emmc>, <&qos_nand>,
234 <&qos_sdio>, <&qos_sfc>;
235 };
236 pd_vpu@PX30_PD_VPU {
237 reg = <PX30_PD_VPU>;
238 clocks = <&cru ACLK_VPU>,
239 <&cru HCLK_VPU>,
240 <&cru SCLK_CORE_VPU>;
241 pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
242 };
243 pd_vo@PX30_PD_VO {
244 reg = <PX30_PD_VO>;
245 clocks = <&cru ACLK_RGA>,
246 <&cru ACLK_VOPB>,
247 <&cru ACLK_VOPL>,
248 <&cru DCLK_VOPB>,
249 <&cru DCLK_VOPL>,
250 <&cru HCLK_RGA>,
251 <&cru HCLK_VOPB>,
252 <&cru HCLK_VOPL>,
253 <&cru PCLK_MIPI_DSI>,
254 <&cru SCLK_RGA_CORE>,
255 <&cru SCLK_VOPB_PWM>;
256 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
257 <&qos_vop_m0>, <&qos_vop_m1>;
258 };
259 pd_vi@PX30_PD_VI {
260 reg = <PX30_PD_VI>;
261 clocks = <&cru ACLK_CIF>,
262 <&cru ACLK_ISP>,
263 <&cru HCLK_CIF>,
264 <&cru HCLK_ISP>,
265 <&cru SCLK_ISP>;
266 pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
267 <&qos_isp_wr>, <&qos_isp_m1>,
268 <&qos_vip>;
269 };
270 pd_gpu@PX30_PD_GPU {
271 reg = <PX30_PD_GPU>;
272 clocks = <&cru SCLK_GPU>;
273 pm_qos = <&qos_gpu>;
274 };
275 };
276 };
278 pmugrf: syscon@ff010000 {
279 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
280 reg = <0x0 0xff010000 0x0 0x1000>;
281 #address-cells = <1>;
282 #size-cells = <1>;
284 pmu_io_domains: io-domains {
285 compatible = "rockchip,px30-pmu-io-voltage-domain";
286 status = "disabled";
287 };
289 reboot-mode {
290 compatible = "syscon-reboot-mode";
291 offset = <0x200>;
292 mode-bootloader = <BOOT_BL_DOWNLOAD>;
293 mode-fastboot = <BOOT_FASTBOOT>;
294 mode-loader = <BOOT_BL_DOWNLOAD>;
295 mode-normal = <BOOT_NORMAL>;
296 mode-recovery = <BOOT_RECOVERY>;
297 };
298 };
300 uart0: serial@ff030000 {
301 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
302 reg = <0x0 0xff030000 0x0 0x100>;
303 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
305 clock-names = "baudclk", "apb_pclk";
306 dmas = <&dmac 0>, <&dmac 1>;
307 dma-names = "tx", "rx";
308 reg-shift = <2>;
309 reg-io-width = <4>;
310 pinctrl-names = "default";
311 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
312 status = "disabled";
313 };
315 i2s1_2ch: i2s@ff070000 {
316 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
317 reg = <0x0 0xff070000 0x0 0x1000>;
318 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
320 clock-names = "i2s_clk", "i2s_hclk";
321 dmas = <&dmac 18>, <&dmac 19>;
322 dma-names = "tx", "rx";
323 pinctrl-names = "default";
324 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
325 &i2s1_2ch_sdi &i2s1_2ch_sdo>;
326 #sound-dai-cells = <0>;
327 status = "disabled";
328 };
330 i2s2_2ch: i2s@ff080000 {
331 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
332 reg = <0x0 0xff080000 0x0 0x1000>;
333 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
335 clock-names = "i2s_clk", "i2s_hclk";
336 dmas = <&dmac 20>, <&dmac 21>;
337 dma-names = "tx", "rx";
338 pinctrl-names = "default";
339 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
340 &i2s2_2ch_sdi &i2s2_2ch_sdo>;
341 #sound-dai-cells = <0>;
342 status = "disabled";
343 };
345 gic: interrupt-controller@ff131000 {
346 compatible = "arm,gic-400";
347 #interrupt-cells = <3>;
348 #address-cells = <0>;
349 interrupt-controller;
350 reg = <0x0 0xff131000 0 0x1000>,
351 <0x0 0xff132000 0 0x2000>,
352 <0x0 0xff134000 0 0x2000>,
353 <0x0 0xff136000 0 0x2000>;
354 interrupts = <GIC_PPI 9
355 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
356 };
358 grf: syscon@ff140000 {
359 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
360 reg = <0x0 0xff140000 0x0 0x1000>;
361 #address-cells = <1>;
362 #size-cells = <1>;
364 io_domains: io-domains {
365 compatible = "rockchip,px30-io-voltage-domain";
366 status = "disabled";
367 };
368 };
370 uart1: serial@ff158000 {
371 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
372 reg = <0x0 0xff158000 0x0 0x100>;
373 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
375 clock-names = "baudclk", "apb_pclk";
376 dmas = <&dmac 2>, <&dmac 3>;
377 dma-names = "tx", "rx";
378 reg-shift = <2>;
379 reg-io-width = <4>;
380 pinctrl-names = "default";
381 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
382 status = "disabled";
383 };
385 uart2: serial@ff160000 {
386 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
387 reg = <0x0 0xff160000 0x0 0x100>;
388 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
389 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
390 clock-names = "baudclk", "apb_pclk";
391 dmas = <&dmac 4>, <&dmac 5>;
392 dma-names = "tx", "rx";
393 reg-shift = <2>;
394 reg-io-width = <4>;
395 pinctrl-names = "default";
396 pinctrl-0 = <&uart2m0_xfer>;
397 status = "disabled";
398 };
400 uart3: serial@ff168000 {
401 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
402 reg = <0x0 0xff168000 0x0 0x100>;
403 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
405 clock-names = "baudclk", "apb_pclk";
406 dmas = <&dmac 6>, <&dmac 7>;
407 dma-names = "tx", "rx";
408 reg-shift = <2>;
409 reg-io-width = <4>;
410 pinctrl-names = "default";
411 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
412 status = "disabled";
413 };
415 uart4: serial@ff170000 {
416 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
417 reg = <0x0 0xff170000 0x0 0x100>;
418 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
420 clock-names = "baudclk", "apb_pclk";
421 dmas = <&dmac 8>, <&dmac 9>;
422 dma-names = "tx", "rx";
423 reg-shift = <2>;
424 reg-io-width = <4>;
425 pinctrl-names = "default";
426 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
427 status = "disabled";
428 };
430 uart5: serial@ff178000 {
431 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
432 reg = <0x0 0xff178000 0x0 0x100>;
433 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
435 clock-names = "baudclk", "apb_pclk";
436 dmas = <&dmac 10>, <&dmac 11>;
437 dma-names = "tx", "rx";
438 reg-shift = <2>;
439 reg-io-width = <4>;
440 pinctrl-names = "default";
441 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
442 status = "disabled";
443 };
445 i2c0: i2c@ff180000 {
446 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
447 reg = <0x0 0xff180000 0x0 0x1000>;
448 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
449 clock-names = "i2c", "pclk";
450 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
451 pinctrl-names = "default";
452 pinctrl-0 = <&i2c0_xfer>;
453 #address-cells = <1>;
454 #size-cells = <0>;
455 status = "disabled";
456 };
458 i2c1: i2c@ff190000 {
459 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
460 reg = <0x0 0xff190000 0x0 0x1000>;
461 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
462 clock-names = "i2c", "pclk";
463 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
464 pinctrl-names = "default";
465 pinctrl-0 = <&i2c1_xfer>;
466 #address-cells = <1>;
467 #size-cells = <0>;
468 status = "disabled";
469 };
471 i2c2: i2c@ff1a0000 {
472 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
473 reg = <0x0 0xff1a0000 0x0 0x1000>;
474 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
475 clock-names = "i2c", "pclk";
476 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
477 pinctrl-names = "default";
478 pinctrl-0 = <&i2c2_xfer>;
479 #address-cells = <1>;
480 #size-cells = <0>;
481 status = "disabled";
482 };
484 i2c3: i2c@ff1b0000 {
485 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
486 reg = <0x0 0xff1b0000 0x0 0x1000>;
487 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
488 clock-names = "i2c", "pclk";
489 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
490 pinctrl-names = "default";
491 pinctrl-0 = <&i2c3_xfer>;
492 #address-cells = <1>;
493 #size-cells = <0>;
494 status = "disabled";
495 };
497 spi0: spi@ff1d0000 {
498 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
499 reg = <0x0 0xff1d0000 0x0 0x1000>;
500 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
502 clock-names = "spiclk", "apb_pclk";
503 dmas = <&dmac 12>, <&dmac 13>;
504 dma-names = "tx", "rx";
505 pinctrl-names = "default";
506 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
507 #address-cells = <1>;
508 #size-cells = <0>;
509 status = "disabled";
510 };
512 spi1: spi@ff1d8000 {
513 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
514 reg = <0x0 0xff1d8000 0x0 0x1000>;
515 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
517 clock-names = "spiclk", "apb_pclk";
518 dmas = <&dmac 14>, <&dmac 15>;
519 dma-names = "tx", "rx";
520 pinctrl-names = "default";
521 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
522 #address-cells = <1>;
523 #size-cells = <0>;
524 status = "disabled";
525 };
527 wdt: watchdog@ff1e0000 {
528 compatible = "snps,dw-wdt";
529 reg = <0x0 0xff1e0000 0x0 0x100>;
530 clocks = <&cru PCLK_WDT_NS>;
531 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
532 status = "disabled";
533 };
535 pwm0: pwm@ff200000 {
536 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
537 reg = <0x0 0xff200000 0x0 0x10>;
538 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
539 clock-names = "pwm", "pclk";
540 pinctrl-names = "default";
541 pinctrl-0 = <&pwm0_pin>;
542 #pwm-cells = <3>;
543 status = "disabled";
544 };
546 pwm1: pwm@ff200010 {
547 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
548 reg = <0x0 0xff200010 0x0 0x10>;
549 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
550 clock-names = "pwm", "pclk";
551 pinctrl-names = "default";
552 pinctrl-0 = <&pwm1_pin>;
553 #pwm-cells = <3>;
554 status = "disabled";
555 };
557 pwm2: pwm@ff200020 {
558 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
559 reg = <0x0 0xff200020 0x0 0x10>;
560 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
561 clock-names = "pwm", "pclk";
562 pinctrl-names = "default";
563 pinctrl-0 = <&pwm2_pin>;
564 #pwm-cells = <3>;
565 status = "disabled";
566 };
568 pwm3: pwm@ff200030 {
569 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
570 reg = <0x0 0xff200030 0x0 0x10>;
571 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
572 clock-names = "pwm", "pclk";
573 pinctrl-names = "default";
574 pinctrl-0 = <&pwm3_pin>;
575 #pwm-cells = <3>;
576 status = "disabled";
577 };
579 pwm4: pwm@ff208000 {
580 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
581 reg = <0x0 0xff208000 0x0 0x10>;
582 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
583 clock-names = "pwm", "pclk";
584 pinctrl-names = "default";
585 pinctrl-0 = <&pwm4_pin>;
586 #pwm-cells = <3>;
587 status = "disabled";
588 };
590 pwm5: pwm@ff208010 {
591 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
592 reg = <0x0 0xff208010 0x0 0x10>;
593 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
594 clock-names = "pwm", "pclk";
595 pinctrl-names = "default";
596 pinctrl-0 = <&pwm5_pin>;
597 #pwm-cells = <3>;
598 status = "disabled";
599 };
601 pwm6: pwm@ff208020 {
602 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
603 reg = <0x0 0xff208020 0x0 0x10>;
604 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
605 clock-names = "pwm", "pclk";
606 pinctrl-names = "default";
607 pinctrl-0 = <&pwm6_pin>;
608 #pwm-cells = <3>;
609 status = "disabled";
610 };
612 pwm7: pwm@ff208030 {
613 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
614 reg = <0x0 0xff208030 0x0 0x10>;
615 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
616 clock-names = "pwm", "pclk";
617 pinctrl-names = "default";
618 pinctrl-0 = <&pwm7_pin>;
619 #pwm-cells = <3>;
620 status = "disabled";
621 };
623 rktimer: timer@ff210000 {
624 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
625 reg = <0x0 0xff210000 0x0 0x1000>;
626 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
627 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
628 clock-names = "pclk", "timer";
629 };
631 amba {
632 compatible = "simple-bus";
633 #address-cells = <2>;
634 #size-cells = <2>;
635 ranges;
637 dmac: dmac@ff240000 {
638 compatible = "arm,pl330", "arm,primecell";
639 reg = <0x0 0xff240000 0x0 0x4000>;
640 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
642 clocks = <&cru ACLK_DMAC>;
643 clock-names = "apb_pclk";
644 #dma-cells = <1>;
645 };
646 };
648 saradc: saradc@ff288000 {
649 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
650 reg = <0x0 0xff288000 0x0 0x100>;
651 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
652 #io-channel-cells = <1>;
653 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
654 clock-names = "saradc", "apb_pclk";
655 resets = <&cru SRST_SARADC_P>;
656 reset-names = "saradc-apb";
657 status = "disabled";
658 };
660 otp: nvmem@ff290000 {
661 compatible = "rockchip,px30-otp";
662 reg = <0x0 0xff290000 0x0 0x4000>;
663 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
664 <&cru PCLK_OTP_PHY>;
665 clock-names = "otp", "apb_pclk", "phy";
666 resets = <&cru SRST_OTP_PHY>;
667 reset-names = "phy";
668 #address-cells = <1>;
669 #size-cells = <1>;
671 /* Data cells */
672 cpu_id: id@7 {
673 reg = <0x07 0x10>;
674 };
675 cpu_leakage: cpu-leakage@17 {
676 reg = <0x17 0x1>;
677 };
678 performance: performance@1e {
679 reg = <0x1e 0x1>;
680 bits = <4 3>;
681 };
682 };
684 cru: clock-controller@ff2b0000 {
685 compatible = "rockchip,px30-cru";
686 reg = <0x0 0xff2b0000 0x0 0x1000>;
687 clocks = <&xin24m>, <&pmucru PLL_GPLL>;
688 clock-names = "xin24m", "gpll";
689 rockchip,grf = <&grf>;
690 #clock-cells = <1>;
691 #reset-cells = <1>;
693 assigned-clocks = <&cru PLL_NPLL>,
694 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
695 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
696 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
698 assigned-clock-rates = <1188000000>,
699 <200000000>, <200000000>,
700 <150000000>, <150000000>,
701 <100000000>, <200000000>;
702 };
704 pmucru: clock-controller@ff2bc000 {
705 compatible = "rockchip,px30-pmucru";
706 reg = <0x0 0xff2bc000 0x0 0x1000>;
707 clocks = <&xin24m>;
708 clock-names = "xin24m";
709 rockchip,grf = <&grf>;
710 #clock-cells = <1>;
711 #reset-cells = <1>;
713 assigned-clocks =
714 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
715 <&pmucru SCLK_WIFI_PMU>;
716 assigned-clock-rates =
717 <1200000000>, <100000000>,
718 <26000000>;
719 };
721 usb2phy_grf: syscon@ff2c0000 {
722 compatible = "rockchip,px30-usb2phy-grf", "syscon",
723 "simple-mfd";
724 reg = <0x0 0xff2c0000 0x0 0x10000>;
725 #address-cells = <1>;
726 #size-cells = <1>;
728 u2phy: usb2-phy@100 {
729 compatible = "rockchip,px30-usb2phy";
730 reg = <0x100 0x20>;
731 clocks = <&pmucru SCLK_USBPHY_REF>;
732 clock-names = "phyclk";
733 #clock-cells = <0>;
734 assigned-clocks = <&cru USB480M>;
735 assigned-clock-parents = <&u2phy>;
736 clock-output-names = "usb480m_phy";
737 status = "disabled";
739 u2phy_host: host-port {
740 #phy-cells = <0>;
741 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
742 interrupt-names = "linestate";
743 status = "disabled";
744 };
746 u2phy_otg: otg-port {
747 #phy-cells = <0>;
748 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
751 interrupt-names = "otg-bvalid", "otg-id",
752 "linestate";
753 status = "disabled";
754 };
755 };
756 };
758 usb20_otg: usb@ff300000 {
759 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
760 "snps,dwc2";
761 reg = <0x0 0xff300000 0x0 0x40000>;
762 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&cru HCLK_OTG>;
764 clock-names = "otg";
765 dr_mode = "otg";
766 g-np-tx-fifo-size = <16>;
767 g-rx-fifo-size = <280>;
768 g-tx-fifo-size = <256 128 128 64 32 16>;
769 g-use-dma;
770 phys = <&u2phy_otg>;
771 phy-names = "usb2-phy";
772 power-domains = <&power PX30_PD_USB>;
773 status = "disabled";
774 };
776 usb_host0_ehci: usb@ff340000 {
777 compatible = "generic-ehci";
778 reg = <0x0 0xff340000 0x0 0x10000>;
779 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
780 clocks = <&cru HCLK_HOST>;
781 clock-names = "usbhost";
782 phys = <&u2phy_host>;
783 phy-names = "usb";
784 power-domains = <&power PX30_PD_USB>;
785 status = "disabled";
786 };
788 usb_host0_ohci: usb@ff350000 {
789 compatible = "generic-ohci";
790 reg = <0x0 0xff350000 0x0 0x10000>;
791 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&cru HCLK_HOST>;
793 clock-names = "usbhost";
794 phys = <&u2phy_host>;
795 phy-names = "usb";
796 power-domains = <&power PX30_PD_USB>;
797 status = "disabled";
798 };
800 gmac: ethernet@ff360000 {
801 compatible = "rockchip,px30-gmac";
802 reg = <0x0 0xff360000 0x0 0x10000>;
803 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
804 interrupt-names = "macirq";
805 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
806 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
807 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
808 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
809 clock-names = "stmmaceth", "mac_clk_rx",
810 "mac_clk_tx", "clk_mac_ref",
811 "clk_mac_refout", "aclk_mac",
812 "pclk_mac", "clk_mac_speed";
813 rockchip,grf = <&grf>;
814 phy-mode = "rmii";
815 pinctrl-names = "default";
816 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
817 power-domains = <&power PX30_PD_GMAC>;
818 resets = <&cru SRST_GMAC_A>;
819 reset-names = "stmmaceth";
820 status = "disabled";
821 };
823 sdmmc: dwmmc@ff370000 {
824 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
825 reg = <0x0 0xff370000 0x0 0x4000>;
826 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
827 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
828 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
829 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
830 fifo-depth = <0x100>;
831 max-frequency = <150000000>;
832 pinctrl-names = "default";
833 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
834 power-domains = <&power PX30_PD_SDCARD>;
835 status = "disabled";
836 };
838 sdio: dwmmc@ff380000 {
839 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
840 reg = <0x0 0xff380000 0x0 0x4000>;
841 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
842 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
843 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
844 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
845 fifo-depth = <0x100>;
846 max-frequency = <150000000>;
847 pinctrl-names = "default";
848 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
849 power-domains = <&power PX30_PD_MMC_NAND>;
850 status = "disabled";
851 };
853 emmc: dwmmc@ff390000 {
854 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
855 reg = <0x0 0xff390000 0x0 0x4000>;
856 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
857 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
858 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
859 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
860 fifo-depth = <0x100>;
861 max-frequency = <150000000>;
862 pinctrl-names = "default";
863 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
864 power-domains = <&power PX30_PD_MMC_NAND>;
865 status = "disabled";
866 };
868 vopb: vop@ff460000 {
869 compatible = "rockchip,px30-vop-big";
870 reg = <0x0 0xff460000 0x0 0xefc>;
871 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
872 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
873 <&cru HCLK_VOPB>;
874 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
875 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
876 reset-names = "axi", "ahb", "dclk";
877 iommus = <&vopb_mmu>;
878 power-domains = <&power PX30_PD_VO>;
879 rockchip,grf = <&grf>;
880 status = "disabled";
882 vopb_out: port {
883 #address-cells = <1>;
884 #size-cells = <0>;
885 };
886 };
888 vopb_mmu: iommu@ff460f00 {
889 compatible = "rockchip,iommu";
890 reg = <0x0 0xff460f00 0x0 0x100>;
891 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
892 interrupt-names = "vopb_mmu";
893 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
894 clock-names = "aclk", "iface";
895 power-domains = <&power PX30_PD_VO>;
896 #iommu-cells = <0>;
897 status = "disabled";
898 };
900 vopl: vop@ff470000 {
901 compatible = "rockchip,px30-vop-lit";
902 reg = <0x0 0xff470000 0x0 0xefc>;
903 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
904 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
905 <&cru HCLK_VOPL>;
906 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
907 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
908 reset-names = "axi", "ahb", "dclk";
909 iommus = <&vopl_mmu>;
910 power-domains = <&power PX30_PD_VO>;
911 rockchip,grf = <&grf>;
912 status = "disabled";
914 vopl_out: port {
915 #address-cells = <1>;
916 #size-cells = <0>;
917 };
918 };
920 vopl_mmu: iommu@ff470f00 {
921 compatible = "rockchip,iommu";
922 reg = <0x0 0xff470f00 0x0 0x100>;
923 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
924 interrupt-names = "vopl_mmu";
925 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
926 clock-names = "aclk", "iface";
927 power-domains = <&power PX30_PD_VO>;
928 #iommu-cells = <0>;
929 status = "disabled";
930 };
932 qos_gmac: qos@ff518000 {
933 compatible = "syscon";
934 reg = <0x0 0xff518000 0x0 0x20>;
935 };
937 qos_gpu: qos@ff520000 {
938 compatible = "syscon";
939 reg = <0x0 0xff520000 0x0 0x20>;
940 };
942 qos_sdmmc: qos@ff52c000 {
943 compatible = "syscon";
944 reg = <0x0 0xff52c000 0x0 0x20>;
945 };
947 qos_emmc: qos@ff538000 {
948 compatible = "syscon";
949 reg = <0x0 0xff538000 0x0 0x20>;
950 };
952 qos_nand: qos@ff538080 {
953 compatible = "syscon";
954 reg = <0x0 0xff538080 0x0 0x20>;
955 };
957 qos_sdio: qos@ff538100 {
958 compatible = "syscon";
959 reg = <0x0 0xff538100 0x0 0x20>;
960 };
962 qos_sfc: qos@ff538180 {
963 compatible = "syscon";
964 reg = <0x0 0xff538180 0x0 0x20>;
965 };
967 qos_usb_host: qos@ff540000 {
968 compatible = "syscon";
969 reg = <0x0 0xff540000 0x0 0x20>;
970 };
972 qos_usb_otg: qos@ff540080 {
973 compatible = "syscon";
974 reg = <0x0 0xff540080 0x0 0x20>;
975 };
977 qos_isp_128: qos@ff548000 {
978 compatible = "syscon";
979 reg = <0x0 0xff548000 0x0 0x20>;
980 };
982 qos_isp_rd: qos@ff548080 {
983 compatible = "syscon";
984 reg = <0x0 0xff548080 0x0 0x20>;
985 };
987 qos_isp_wr: qos@ff548100 {
988 compatible = "syscon";
989 reg = <0x0 0xff548100 0x0 0x20>;
990 };
992 qos_isp_m1: qos@ff548180 {
993 compatible = "syscon";
994 reg = <0x0 0xff548180 0x0 0x20>;
995 };
997 qos_vip: qos@ff548200 {
998 compatible = "syscon";
999 reg = <0x0 0xff548200 0x0 0x20>;
1000 };
1002 qos_rga_rd: qos@ff550000 {
1003 compatible = "syscon";
1004 reg = <0x0 0xff550000 0x0 0x20>;
1005 };
1007 qos_rga_wr: qos@ff550080 {
1008 compatible = "syscon";
1009 reg = <0x0 0xff550080 0x0 0x20>;
1010 };
1012 qos_vop_m0: qos@ff550100 {
1013 compatible = "syscon";
1014 reg = <0x0 0xff550100 0x0 0x20>;
1015 };
1017 qos_vop_m1: qos@ff550180 {
1018 compatible = "syscon";
1019 reg = <0x0 0xff550180 0x0 0x20>;
1020 };
1022 qos_vpu: qos@ff558000 {
1023 compatible = "syscon";
1024 reg = <0x0 0xff558000 0x0 0x20>;
1025 };
1027 qos_vpu_r128: qos@ff558080 {
1028 compatible = "syscon";
1029 reg = <0x0 0xff558080 0x0 0x20>;
1030 };
1032 pinctrl: pinctrl {
1033 compatible = "rockchip,px30-pinctrl";
1034 rockchip,grf = <&grf>;
1035 rockchip,pmu = <&pmugrf>;
1036 #address-cells = <2>;
1037 #size-cells = <2>;
1038 ranges;
1040 gpio0: gpio0@ff040000 {
1041 compatible = "rockchip,gpio-bank";
1042 reg = <0x0 0xff040000 0x0 0x100>;
1043 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1044 clocks = <&pmucru PCLK_GPIO0_PMU>;
1045 gpio-controller;
1046 #gpio-cells = <2>;
1048 interrupt-controller;
1049 #interrupt-cells = <2>;
1050 };
1052 gpio1: gpio1@ff250000 {
1053 compatible = "rockchip,gpio-bank";
1054 reg = <0x0 0xff250000 0x0 0x100>;
1055 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1056 clocks = <&cru PCLK_GPIO1>;
1057 gpio-controller;
1058 #gpio-cells = <2>;
1060 interrupt-controller;
1061 #interrupt-cells = <2>;
1062 };
1064 gpio2: gpio2@ff260000 {
1065 compatible = "rockchip,gpio-bank";
1066 reg = <0x0 0xff260000 0x0 0x100>;
1067 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1068 clocks = <&cru PCLK_GPIO2>;
1069 gpio-controller;
1070 #gpio-cells = <2>;
1072 interrupt-controller;
1073 #interrupt-cells = <2>;
1074 };
1076 gpio3: gpio3@ff270000 {
1077 compatible = "rockchip,gpio-bank";
1078 reg = <0x0 0xff270000 0x0 0x100>;
1079 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1080 clocks = <&cru PCLK_GPIO3>;
1081 gpio-controller;
1082 #gpio-cells = <2>;
1084 interrupt-controller;
1085 #interrupt-cells = <2>;
1086 };
1088 pcfg_pull_up: pcfg-pull-up {
1089 bias-pull-up;
1090 };
1092 pcfg_pull_down: pcfg-pull-down {
1093 bias-pull-down;
1094 };
1096 pcfg_pull_none: pcfg-pull-none {
1097 bias-disable;
1098 };
1100 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1101 bias-disable;
1102 drive-strength = <2>;
1103 };
1105 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1106 bias-pull-up;
1107 drive-strength = <2>;
1108 };
1110 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1111 bias-pull-up;
1112 drive-strength = <4>;
1113 };
1115 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1116 bias-disable;
1117 drive-strength = <4>;
1118 };
1120 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1121 bias-pull-down;
1122 drive-strength = <4>;
1123 };
1125 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1126 bias-disable;
1127 drive-strength = <8>;
1128 };
1130 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1131 bias-pull-up;
1132 drive-strength = <8>;
1133 };
1135 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1136 bias-disable;
1137 drive-strength = <12>;
1138 };
1140 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1141 bias-pull-up;
1142 drive-strength = <12>;
1143 };
1145 pcfg_pull_none_smt: pcfg-pull-none-smt {
1146 bias-disable;
1147 input-schmitt-enable;
1148 };
1150 pcfg_output_high: pcfg-output-high {
1151 output-high;
1152 };
1154 pcfg_output_low: pcfg-output-low {
1155 output-low;
1156 };
1158 pcfg_input_high: pcfg-input-high {
1159 bias-pull-up;
1160 input-enable;
1161 };
1163 pcfg_input: pcfg-input {
1164 input-enable;
1165 };
1167 i2c0 {
1168 i2c0_xfer: i2c0-xfer {
1169 rockchip,pins =
1170 <0 RK_PB0 1 &pcfg_pull_none_smt>,
1171 <0 RK_PB1 1 &pcfg_pull_none_smt>;
1172 };
1173 };
1175 i2c1 {
1176 i2c1_xfer: i2c1-xfer {
1177 rockchip,pins =
1178 <0 RK_PC2 1 &pcfg_pull_none_smt>,
1179 <0 RK_PC3 1 &pcfg_pull_none_smt>;
1180 };
1181 };
1183 i2c2 {
1184 i2c2_xfer: i2c2-xfer {
1185 rockchip,pins =
1186 <2 RK_PB7 2 &pcfg_pull_none_smt>,
1187 <2 RK_PC0 2 &pcfg_pull_none_smt>;
1188 };
1189 };
1191 i2c3 {
1192 i2c3_xfer: i2c3-xfer {
1193 rockchip,pins =
1194 <1 RK_PB4 4 &pcfg_pull_none_smt>,
1195 <1 RK_PB5 4 &pcfg_pull_none_smt>;
1196 };
1197 };
1199 tsadc {
1200 tsadc_otp_gpio: tsadc-otp-gpio {
1201 rockchip,pins =
1202 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1203 };
1205 tsadc_otp_out: tsadc-otp-out {
1206 rockchip,pins =
1207 <0 RK_PA6 1 &pcfg_pull_none>;
1208 };
1209 };
1211 uart0 {
1212 uart0_xfer: uart0-xfer {
1213 rockchip,pins =
1214 <0 RK_PB2 1 &pcfg_pull_up>,
1215 <0 RK_PB3 1 &pcfg_pull_up>;
1216 };
1218 uart0_cts: uart0-cts {
1219 rockchip,pins =
1220 <0 RK_PB4 1 &pcfg_pull_none>;
1221 };
1223 uart0_rts: uart0-rts {
1224 rockchip,pins =
1225 <0 RK_PB5 1 &pcfg_pull_none>;
1226 };
1227 };
1229 uart1 {
1230 uart1_xfer: uart1-xfer {
1231 rockchip,pins =
1232 <1 RK_PC1 1 &pcfg_pull_up>,
1233 <1 RK_PC0 1 &pcfg_pull_up>;
1234 };
1236 uart1_cts: uart1-cts {
1237 rockchip,pins =
1238 <1 RK_PC2 1 &pcfg_pull_none>;
1239 };
1241 uart1_rts: uart1-rts {
1242 rockchip,pins =
1243 <1 RK_PC3 1 &pcfg_pull_none>;
1244 };
1245 };
1247 uart2-m0 {
1248 uart2m0_xfer: uart2m0-xfer {
1249 rockchip,pins =
1250 <1 RK_PD2 2 &pcfg_pull_up>,
1251 <1 RK_PD3 2 &pcfg_pull_up>;
1252 };
1253 };
1255 uart2-m1 {
1256 uart2m1_xfer: uart2m1-xfer {
1257 rockchip,pins =
1258 <2 RK_PB4 2 &pcfg_pull_up>,
1259 <2 RK_PB6 2 &pcfg_pull_up>;
1260 };
1261 };
1263 uart3-m0 {
1264 uart3m0_xfer: uart3m0-xfer {
1265 rockchip,pins =
1266 <0 RK_PC0 2 &pcfg_pull_up>,
1267 <0 RK_PC1 2 &pcfg_pull_up>;
1268 };
1270 uart3m0_cts: uart3m0-cts {
1271 rockchip,pins =
1272 <0 RK_PC2 2 &pcfg_pull_none>;
1273 };
1275 uart3m0_rts: uart3m0-rts {
1276 rockchip,pins =
1277 <0 RK_PC3 2 &pcfg_pull_none>;
1278 };
1279 };
1281 uart3-m1 {
1282 uart3m1_xfer: uart3m1-xfer {
1283 rockchip,pins =
1284 <1 RK_PB6 2 &pcfg_pull_up>,
1285 <1 RK_PB7 2 &pcfg_pull_up>;
1286 };
1288 uart3m1_cts: uart3m1-cts {
1289 rockchip,pins =
1290 <1 RK_PB4 2 &pcfg_pull_none>;
1291 };
1293 uart3m1_rts: uart3m1-rts {
1294 rockchip,pins =
1295 <1 RK_PB5 2 &pcfg_pull_none>;
1296 };
1297 };
1299 uart4 {
1300 uart4_xfer: uart4-xfer {
1301 rockchip,pins =
1302 <1 RK_PD4 2 &pcfg_pull_up>,
1303 <1 RK_PD5 2 &pcfg_pull_up>;
1304 };
1306 uart4_cts: uart4-cts {
1307 rockchip,pins =
1308 <1 RK_PD6 2 &pcfg_pull_none>;
1309 };
1311 uart4_rts: uart4-rts {
1312 rockchip,pins =
1313 <1 RK_PD7 2 &pcfg_pull_none>;
1314 };
1315 };
1317 uart5 {
1318 uart5_xfer: uart5-xfer {
1319 rockchip,pins =
1320 <3 RK_PA2 4 &pcfg_pull_up>,
1321 <3 RK_PA1 4 &pcfg_pull_up>;
1322 };
1324 uart5_cts: uart5-cts {
1325 rockchip,pins =
1326 <3 RK_PA3 4 &pcfg_pull_none>;
1327 };
1329 uart5_rts: uart5-rts {
1330 rockchip,pins =
1331 <3 RK_PA5 4 &pcfg_pull_none>;
1332 };
1333 };
1335 spi0 {
1336 spi0_clk: spi0-clk {
1337 rockchip,pins =
1338 <1 RK_PB7 3 &pcfg_pull_up_4ma>;
1339 };
1341 spi0_csn: spi0-csn {
1342 rockchip,pins =
1343 <1 RK_PB6 3 &pcfg_pull_up_4ma>;
1344 };
1346 spi0_miso: spi0-miso {
1347 rockchip,pins =
1348 <1 RK_PB5 3 &pcfg_pull_up_4ma>;
1349 };
1351 spi0_mosi: spi0-mosi {
1352 rockchip,pins =
1353 <1 RK_PB4 3 &pcfg_pull_up_4ma>;
1354 };
1356 spi0_clk_hs: spi0-clk-hs {
1357 rockchip,pins =
1358 <1 RK_PB7 3 &pcfg_pull_up_8ma>;
1359 };
1361 spi0_miso_hs: spi0-miso-hs {
1362 rockchip,pins =
1363 <1 RK_PB5 3 &pcfg_pull_up_8ma>;
1364 };
1366 spi0_mosi_hs: spi0-mosi-hs {
1367 rockchip,pins =
1368 <1 RK_PB4 3 &pcfg_pull_up_8ma>;
1369 };
1370 };
1372 spi1 {
1373 spi1_clk: spi1-clk {
1374 rockchip,pins =
1375 <3 RK_PB7 4 &pcfg_pull_up_4ma>;
1376 };
1378 spi1_csn0: spi1-csn0 {
1379 rockchip,pins =
1380 <3 RK_PB1 4 &pcfg_pull_up_4ma>;
1381 };
1383 spi1_csn1: spi1-csn1 {
1384 rockchip,pins =
1385 <3 RK_PB2 2 &pcfg_pull_up_4ma>;
1386 };
1388 spi1_miso: spi1-miso {
1389 rockchip,pins =
1390 <3 RK_PB6 4 &pcfg_pull_up_4ma>;
1391 };
1393 spi1_mosi: spi1-mosi {
1394 rockchip,pins =
1395 <3 RK_PB4 4 &pcfg_pull_up_4ma>;
1396 };
1398 spi1_clk_hs: spi1-clk-hs {
1399 rockchip,pins =
1400 <3 RK_PB7 4 &pcfg_pull_up_8ma>;
1401 };
1403 spi1_miso_hs: spi1-miso-hs {
1404 rockchip,pins =
1405 <3 RK_PB6 4 &pcfg_pull_up_8ma>;
1406 };
1408 spi1_mosi_hs: spi1-mosi-hs {
1409 rockchip,pins =
1410 <3 RK_PB4 4 &pcfg_pull_up_8ma>;
1411 };
1412 };
1414 pdm {
1415 pdm_clk0m0: pdm-clk0m0 {
1416 rockchip,pins =
1417 <3 RK_PC6 2 &pcfg_pull_none>;
1418 };
1420 pdm_clk0m1: pdm-clk0m1 {
1421 rockchip,pins =
1422 <2 RK_PC6 1 &pcfg_pull_none>;
1423 };
1425 pdm_clk1: pdm-clk1 {
1426 rockchip,pins =
1427 <3 RK_PC7 2 &pcfg_pull_none>;
1428 };
1430 pdm_sdi0m0: pdm-sdi0m0 {
1431 rockchip,pins =
1432 <3 RK_PD3 2 &pcfg_pull_none>;
1433 };
1435 pdm_sdi0m1: pdm-sdi0m1 {
1436 rockchip,pins =
1437 <2 RK_PC5 2 &pcfg_pull_none>;
1438 };
1440 pdm_sdi1: pdm-sdi1 {
1441 rockchip,pins =
1442 <3 RK_PD0 2 &pcfg_pull_none>;
1443 };
1445 pdm_sdi2: pdm-sdi2 {
1446 rockchip,pins =
1447 <3 RK_PD1 2 &pcfg_pull_none>;
1448 };
1450 pdm_sdi3: pdm-sdi3 {
1451 rockchip,pins =
1452 <3 RK_PD2 2 &pcfg_pull_none>;
1453 };
1455 pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1456 rockchip,pins =
1457 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1458 };
1460 pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1461 rockchip,pins =
1462 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1463 };
1465 pdm_clk1_sleep: pdm-clk1-sleep {
1466 rockchip,pins =
1467 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1468 };
1470 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1471 rockchip,pins =
1472 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>;
1473 };
1475 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1476 rockchip,pins =
1477 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1478 };
1480 pdm_sdi1_sleep: pdm-sdi1-sleep {
1481 rockchip,pins =
1482 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>;
1483 };
1485 pdm_sdi2_sleep: pdm-sdi2-sleep {
1486 rockchip,pins =
1487 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1488 };
1490 pdm_sdi3_sleep: pdm-sdi3-sleep {
1491 rockchip,pins =
1492 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>;
1493 };
1494 };
1496 i2s0 {
1497 i2s0_8ch_mclk: i2s0-8ch-mclk {
1498 rockchip,pins =
1499 <3 RK_PC1 2 &pcfg_pull_none>;
1500 };
1502 i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1503 rockchip,pins =
1504 <3 RK_PC3 2 &pcfg_pull_none>;
1505 };
1507 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1508 rockchip,pins =
1509 <3 RK_PB4 2 &pcfg_pull_none>;
1510 };
1512 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1513 rockchip,pins =
1514 <3 RK_PC2 2 &pcfg_pull_none>;
1515 };
1517 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1518 rockchip,pins =
1519 <3 RK_PB5 2 &pcfg_pull_none>;
1520 };
1522 i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1523 rockchip,pins =
1524 <3 RK_PC4 2 &pcfg_pull_none>;
1525 };
1527 i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1528 rockchip,pins =
1529 <3 RK_PC0 2 &pcfg_pull_none>;
1530 };
1532 i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1533 rockchip,pins =
1534 <3 RK_PB7 2 &pcfg_pull_none>;
1535 };
1537 i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1538 rockchip,pins =
1539 <3 RK_PB6 2 &pcfg_pull_none>;
1540 };
1542 i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1543 rockchip,pins =
1544 <3 RK_PC5 2 &pcfg_pull_none>;
1545 };
1547 i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1548 rockchip,pins =
1549 <3 RK_PB3 2 &pcfg_pull_none>;
1550 };
1552 i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1553 rockchip,pins =
1554 <3 RK_PB1 2 &pcfg_pull_none>;
1555 };
1557 i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1558 rockchip,pins =
1559 <3 RK_PB0 2 &pcfg_pull_none>;
1560 };
1561 };
1563 i2s1 {
1564 i2s1_2ch_mclk: i2s1-2ch-mclk {
1565 rockchip,pins =
1566 <2 RK_PC3 1 &pcfg_pull_none>;
1567 };
1569 i2s1_2ch_sclk: i2s1-2ch-sclk {
1570 rockchip,pins =
1571 <2 RK_PC2 1 &pcfg_pull_none>;
1572 };
1574 i2s1_2ch_lrck: i2s1-2ch-lrck {
1575 rockchip,pins =
1576 <2 RK_PC1 1 &pcfg_pull_none>;
1577 };
1579 i2s1_2ch_sdi: i2s1-2ch-sdi {
1580 rockchip,pins =
1581 <2 RK_PC5 1 &pcfg_pull_none>;
1582 };
1584 i2s1_2ch_sdo: i2s1-2ch-sdo {
1585 rockchip,pins =
1586 <2 RK_PC4 1 &pcfg_pull_none>;
1587 };
1588 };
1590 i2s2 {
1591 i2s2_2ch_mclk: i2s2-2ch-mclk {
1592 rockchip,pins =
1593 <3 RK_PA1 2 &pcfg_pull_none>;
1594 };
1596 i2s2_2ch_sclk: i2s2-2ch-sclk {
1597 rockchip,pins =
1598 <3 RK_PA2 2 &pcfg_pull_none>;
1599 };
1601 i2s2_2ch_lrck: i2s2-2ch-lrck {
1602 rockchip,pins =
1603 <3 RK_PA3 2 &pcfg_pull_none>;
1604 };
1606 i2s2_2ch_sdi: i2s2-2ch-sdi {
1607 rockchip,pins =
1608 <3 RK_PA5 2 &pcfg_pull_none>;
1609 };
1611 i2s2_2ch_sdo: i2s2-2ch-sdo {
1612 rockchip,pins =
1613 <3 RK_PA7 2 &pcfg_pull_none>;
1614 };
1615 };
1617 sdmmc {
1618 sdmmc_clk: sdmmc-clk {
1619 rockchip,pins =
1620 <1 RK_PD6 1 &pcfg_pull_none_8ma>;
1621 };
1623 sdmmc_cmd: sdmmc-cmd {
1624 rockchip,pins =
1625 <1 RK_PD7 1 &pcfg_pull_up_8ma>;
1626 };
1628 sdmmc_det: sdmmc-det {
1629 rockchip,pins =
1630 <0 RK_PA3 1 &pcfg_pull_up_8ma>;
1631 };
1633 sdmmc_bus1: sdmmc-bus1 {
1634 rockchip,pins =
1635 <1 RK_PD2 1 &pcfg_pull_up_8ma>;
1636 };
1638 sdmmc_bus4: sdmmc-bus4 {
1639 rockchip,pins =
1640 <1 RK_PD2 1 &pcfg_pull_up_8ma>,
1641 <1 RK_PD3 1 &pcfg_pull_up_8ma>,
1642 <1 RK_PD4 1 &pcfg_pull_up_8ma>,
1643 <1 RK_PD5 1 &pcfg_pull_up_8ma>;
1644 };
1645 };
1647 sdio {
1648 sdio_clk: sdio-clk {
1649 rockchip,pins =
1650 <1 RK_PC5 1 &pcfg_pull_none>;
1651 };
1653 sdio_cmd: sdio-cmd {
1654 rockchip,pins =
1655 <1 RK_PC4 1 &pcfg_pull_up>;
1656 };
1658 sdio_bus4: sdio-bus4 {
1659 rockchip,pins =
1660 <1 RK_PC6 1 &pcfg_pull_up>,
1661 <1 RK_PC7 1 &pcfg_pull_up>,
1662 <1 RK_PD0 1 &pcfg_pull_up>,
1663 <1 RK_PD1 1 &pcfg_pull_up>;
1664 };
1665 };
1667 emmc {
1668 emmc_clk: emmc-clk {
1669 rockchip,pins =
1670 <1 RK_PB1 2 &pcfg_pull_none_8ma>;
1671 };
1673 emmc_cmd: emmc-cmd {
1674 rockchip,pins =
1675 <1 RK_PB2 2 &pcfg_pull_up_8ma>;
1676 };
1678 emmc_rstnout: emmc-rstnout {
1679 rockchip,pins =
1680 <1 RK_PB3 2 &pcfg_pull_none>;
1681 };
1683 emmc_bus1: emmc-bus1 {
1684 rockchip,pins =
1685 <1 RK_PA0 2 &pcfg_pull_up_8ma>;
1686 };
1688 emmc_bus4: emmc-bus4 {
1689 rockchip,pins =
1690 <1 RK_PA0 2 &pcfg_pull_up_8ma>,
1691 <1 RK_PA1 2 &pcfg_pull_up_8ma>,
1692 <1 RK_PA2 2 &pcfg_pull_up_8ma>,
1693 <1 RK_PA3 2 &pcfg_pull_up_8ma>;
1694 };
1696 emmc_bus8: emmc-bus8 {
1697 rockchip,pins =
1698 <1 RK_PA0 2 &pcfg_pull_up_8ma>,
1699 <1 RK_PA1 2 &pcfg_pull_up_8ma>,
1700 <1 RK_PA2 2 &pcfg_pull_up_8ma>,
1701 <1 RK_PA3 2 &pcfg_pull_up_8ma>,
1702 <1 RK_PA4 2 &pcfg_pull_up_8ma>,
1703 <1 RK_PA5 2 &pcfg_pull_up_8ma>,
1704 <1 RK_PA6 2 &pcfg_pull_up_8ma>,
1705 <1 RK_PA7 2 &pcfg_pull_up_8ma>;
1706 };
1707 };
1709 flash {
1710 flash_cs0: flash-cs0 {
1711 rockchip,pins =
1712 <1 RK_PB0 1 &pcfg_pull_none>;
1713 };
1715 flash_rdy: flash-rdy {
1716 rockchip,pins =
1717 <1 RK_PB1 1 &pcfg_pull_none>;
1718 };
1720 flash_dqs: flash-dqs {
1721 rockchip,pins =
1722 <1 RK_PB2 1 &pcfg_pull_none>;
1723 };
1725 flash_ale: flash-ale {
1726 rockchip,pins =
1727 <1 RK_PB3 1 &pcfg_pull_none>;
1728 };
1730 flash_cle: flash-cle {
1731 rockchip,pins =
1732 <1 RK_PB4 1 &pcfg_pull_none>;
1733 };
1735 flash_wrn: flash-wrn {
1736 rockchip,pins =
1737 <1 RK_PB5 1 &pcfg_pull_none>;
1738 };
1740 flash_csl: flash-csl {
1741 rockchip,pins =
1742 <1 RK_PB6 1 &pcfg_pull_none>;
1743 };
1745 flash_rdn: flash-rdn {
1746 rockchip,pins =
1747 <1 RK_PB7 1 &pcfg_pull_none>;
1748 };
1750 flash_bus8: flash-bus8 {
1751 rockchip,pins =
1752 <1 RK_PA0 1 &pcfg_pull_up_12ma>,
1753 <1 RK_PA1 1 &pcfg_pull_up_12ma>,
1754 <1 RK_PA2 1 &pcfg_pull_up_12ma>,
1755 <1 RK_PA3 1 &pcfg_pull_up_12ma>,
1756 <1 RK_PA4 1 &pcfg_pull_up_12ma>,
1757 <1 RK_PA5 1 &pcfg_pull_up_12ma>,
1758 <1 RK_PA6 1 &pcfg_pull_up_12ma>,
1759 <1 RK_PA7 1 &pcfg_pull_up_12ma>;
1760 };
1761 };
1763 lcdc {
1764 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
1765 rockchip,pins =
1766 <3 RK_PA0 1 &pcfg_pull_none_12ma>;
1767 };
1769 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
1770 rockchip,pins =
1771 <3 RK_PA1 1 &pcfg_pull_none_12ma>;
1772 };
1774 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
1775 rockchip,pins =
1776 <3 RK_PA2 1 &pcfg_pull_none_12ma>;
1777 };
1779 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
1780 rockchip,pins =
1781 <3 RK_PA3 1 &pcfg_pull_none_12ma>;
1782 };
1784 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
1785 rockchip,pins =
1786 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
1787 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1788 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
1789 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1790 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1791 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1792 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
1793 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
1794 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
1795 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
1796 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1797 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
1798 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1799 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1800 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1801 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
1802 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
1803 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
1804 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
1805 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
1806 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
1807 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
1808 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
1809 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
1810 };
1812 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
1813 rockchip,pins =
1814 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
1815 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1816 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
1817 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1818 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1819 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1820 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
1821 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
1822 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
1823 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
1824 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1825 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
1826 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1827 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1828 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1829 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
1830 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
1831 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
1832 };
1834 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
1835 rockchip,pins =
1836 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
1837 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1838 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
1839 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1840 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1841 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1842 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
1843 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
1844 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
1845 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
1846 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1847 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
1848 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1849 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1850 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1851 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
1852 };
1854 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
1855 rockchip,pins =
1856 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1857 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1858 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1859 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1860 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1861 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1862 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1863 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1864 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
1865 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
1866 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
1867 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
1868 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
1869 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
1870 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
1871 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
1872 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
1873 };
1875 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
1876 rockchip,pins =
1877 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1878 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1879 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1880 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1881 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1882 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1883 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1884 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1885 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
1886 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
1887 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
1888 };
1890 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
1891 rockchip,pins =
1892 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
1893 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
1894 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
1895 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
1896 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
1897 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
1898 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
1899 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
1900 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
1901 };
1902 };
1904 pwm0 {
1905 pwm0_pin: pwm0-pin {
1906 rockchip,pins =
1907 <0 RK_PB7 1 &pcfg_pull_none>;
1908 };
1909 };
1911 pwm1 {
1912 pwm1_pin: pwm1-pin {
1913 rockchip,pins =
1914 <0 RK_PC0 1 &pcfg_pull_none>;
1915 };
1916 };
1918 pwm2 {
1919 pwm2_pin: pwm2-pin {
1920 rockchip,pins =
1921 <2 RK_PB5 1 &pcfg_pull_none>;
1922 };
1923 };
1925 pwm3 {
1926 pwm3_pin: pwm3-pin {
1927 rockchip,pins =
1928 <0 RK_PC1 1 &pcfg_pull_none>;
1929 };
1930 };
1932 pwm4 {
1933 pwm4_pin: pwm4-pin {
1934 rockchip,pins =
1935 <3 RK_PC2 3 &pcfg_pull_none>;
1936 };
1937 };
1939 pwm5 {
1940 pwm5_pin: pwm5-pin {
1941 rockchip,pins =
1942 <3 RK_PC3 3 &pcfg_pull_none>;
1943 };
1944 };
1946 pwm6 {
1947 pwm6_pin: pwm6-pin {
1948 rockchip,pins =
1949 <3 RK_PC4 3 &pcfg_pull_none>;
1950 };
1951 };
1953 pwm7 {
1954 pwm7_pin: pwm7-pin {
1955 rockchip,pins =
1956 <3 RK_PC5 3 &pcfg_pull_none>;
1957 };
1958 };
1960 gmac {
1961 rmii_pins: rmii-pins {
1962 rockchip,pins =
1963 <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
1964 <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
1965 <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
1966 <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
1967 <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
1968 <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
1969 <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
1970 <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
1971 <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
1972 };
1974 mac_refclk_12ma: mac-refclk-12ma {
1975 rockchip,pins =
1976 <2 RK_PB2 2 &pcfg_pull_none_12ma>;
1977 };
1979 mac_refclk: mac-refclk {
1980 rockchip,pins =
1981 <2 RK_PB2 2 &pcfg_pull_none>;
1982 };
1983 };
1985 cif-m0 {
1986 cif_clkout_m0: cif-clkout-m0 {
1987 rockchip,pins =
1988 <2 RK_PB3 1 &pcfg_pull_none>;
1989 };
1991 dvp_d2d9_m0: dvp-d2d9-m0 {
1992 rockchip,pins =
1993 <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
1994 <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
1995 <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
1996 <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
1997 <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
1998 <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
1999 <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
2000 <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
2001 <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
2002 <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
2003 <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
2004 <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
2005 };
2007 dvp_d0d1_m0: dvp-d0d1-m0 {
2008 rockchip,pins =
2009 <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
2010 <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
2011 };
2013 dvp_d10d11_m0:d10-d11-m0 {
2014 rockchip,pins =
2015 <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
2016 <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
2017 };
2018 };
2020 cif-m1 {
2021 cif_clkout_m1: cif-clkout-m1 {
2022 rockchip,pins =
2023 <3 RK_PD0 3 &pcfg_pull_none>;
2024 };
2026 dvp_d2d9_m1: dvp-d2d9-m1 {
2027 rockchip,pins =
2028 <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
2029 <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
2030 <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
2031 <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
2032 <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
2033 <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
2034 <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
2035 <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
2036 <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
2037 <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
2038 <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
2039 <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
2040 };
2042 dvp_d0d1_m1: dvp-d0d1-m1 {
2043 rockchip,pins =
2044 <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
2045 <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
2046 };
2048 dvp_d10d11_m1:d10-d11-m1 {
2049 rockchip,pins =
2050 <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
2051 <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
2052 };
2053 };
2055 isp {
2056 isp_prelight: isp-prelight {
2057 rockchip,pins =
2058 <3 RK_PD1 4 &pcfg_pull_none>;
2059 };
2060 };
2061 };
2062 };