arch/arm/boot/dts/am335x-evm.dts

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
   4  */
   5 /dts-v1/;
   6
   7 #include "am33xx.dtsi"
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9
  10 / {
  11         model = "TI AM335x EVM";
  12         compatible = "ti,am335x-evm", "ti,am33xx";
  13
  14         cpus {
  15                 cpu@0 {
  16                         cpu0-supply = <&vdd1_reg>;
  17                 };
  18         };
  19
  20         memory@80000000 {
  21                 device_type = "memory";
  22                 reg = <0x80000000 0x10000000>; /* 256 MB */
  23         };
  24
  25         chosen {
  26                 stdout-path = &uart0;
  27         };
  28
  29         vbat: fixedregulator0 {
  30                 compatible = "regulator-fixed";
  31                 regulator-name = "vbat";
  32                 regulator-min-microvolt = <5000000>;
  33                 regulator-max-microvolt = <5000000>;
  34                 regulator-boot-on;
  35         };
  36
  37         lis3_reg: fixedregulator1 {
  38                 compatible = "regulator-fixed";
  39                 regulator-name = "lis3_reg";
  40                 regulator-boot-on;
  41         };
  42
  43         wlan_en_reg: fixedregulator2 {
  44                 compatible = "regulator-fixed";
  45                 regulator-name = "wlan-en-regulator";
  46                 regulator-min-microvolt = <1800000>;
  47                 regulator-max-microvolt = <1800000>;
  48
  49                 /* WLAN_EN GPIO for this board - Bank1, pin16 */
  50                 gpio = <&gpio1 16 0>;
  51
  52                 /* WLAN card specific delay */
  53                 startup-delay-us = <70000>;
  54                 enable-active-high;
  55         };
  56
  57         /* TPS79501 */
  58         v1_8d_reg: fixedregulator-v1_8d {
  59                 compatible = "regulator-fixed";
  60                 regulator-name = "v1_8d";
  61                 vin-supply = <&vbat>;
  62                 regulator-min-microvolt = <1800000>;
  63                 regulator-max-microvolt = <1800000>;
  64         };
  65
  66         /* TPS79501 */
  67         v3_3d_reg: fixedregulator-v3_3d {
  68                 compatible = "regulator-fixed";
  69                 regulator-name = "v3_3d";
  70                 vin-supply = <&vbat>;
  71                 regulator-min-microvolt = <3300000>;
  72                 regulator-max-microvolt = <3300000>;
  73         };
  74
  75         matrix_keypad: matrix_keypad0 {
  76                 compatible = "gpio-matrix-keypad";
  77                 debounce-delay-ms = <5>;
  78                 col-scan-delay-us = <2>;
  79
  80                 row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH         /* Bank1, pin25 */
  81                              &gpio1 26 GPIO_ACTIVE_HIGH         /* Bank1, pin26 */
  82                              &gpio1 27 GPIO_ACTIVE_HIGH>;       /* Bank1, pin27 */
  83
  84                 col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH         /* Bank1, pin21 */
  85                              &gpio1 22 GPIO_ACTIVE_HIGH>;       /* Bank1, pin22 */
  86
  87                 linux,keymap = <0x0000008b      /* MENU */
  88                                 0x0100009e      /* BACK */
  89                                 0x02000069      /* LEFT */
  90                                 0x0001006a      /* RIGHT */
  91                                 0x0101001c      /* ENTER */
  92                                 0x0201006c>;    /* DOWN */
  93         };
  94
  95         gpio_keys: volume_keys0 {
  96                 compatible = "gpio-keys";
  97                 #address-cells = <1>;
  98                 #size-cells = <0>;
  99                 autorepeat;
 100
 101                 switch9 {
 102                         label = "volume-up";
 103                         linux,code = <115>;
 104                         gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
 105                         wakeup-source;
 106                 };
 107
 108                 switch10 {
 109                         label = "volume-down";
 110                         linux,code = <114>;
 111                         gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
 112                         wakeup-source;
 113                 };
 114         };
 115
 116         backlight: backlight {
 117                 compatible = "pwm-backlight";
 118                 pwms = <&ecap0 0 50000 0>;
 119                 brightness-levels = <0 51 53 56 62 75 101 152 255>;
 120                 default-brightness-level = <8>;
 121         };
 122
 123         panel {
 124                 compatible = "tfc,s9700rtwv43tr-01b";
 125
 126                 pinctrl-names = "default";
 127                 pinctrl-0 = <&lcd_pins_s0>;
 128                 backlight = <&backlight>;
 129
 130                 port {
 131                         panel_0: endpoint@0 {
 132                                 remote-endpoint = <&lcdc_0>;
 133                         };
 134                 };
 135         };
 136
 137         sound {
 138                 compatible = "simple-audio-card";
 139                 simple-audio-card,name = "AM335x-EVM";
 140                 simple-audio-card,widgets =
 141                         "Headphone", "Headphone Jack",
 142                         "Line", "Line In";
 143                 simple-audio-card,routing =
 144                         "Headphone Jack",       "HPLOUT",
 145                         "Headphone Jack",       "HPROUT",
 146                         "LINE1L",               "Line In",
 147                         "LINE1R",               "Line In";
 148                 simple-audio-card,format = "dsp_b";
 149                 simple-audio-card,bitclock-master = <&sound_master>;
 150                 simple-audio-card,frame-master = <&sound_master>;
 151                 simple-audio-card,bitclock-inversion;
 152
 153                 simple-audio-card,cpu {
 154                         sound-dai = <&mcasp1>;
 155                 };
 156
 157                 sound_master: simple-audio-card,codec {
 158                         sound-dai = <&tlv320aic3106>;
 159                         system-clock-frequency = <12000000>;
 160                 };
 161         };
 162 };
 163
 164 &am33xx_pinmux {
 165         pinctrl-names = "default";
 166         pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
 167
 168         matrix_keypad_s0: matrix_keypad_s0 {
 169                 pinctrl-single,pins = <
 170                         AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* gpmc_a5.gpio1_21 */
 171                         AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* gpmc_a6.gpio1_22 */
 172                         AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7)       /* gpmc_a9.gpio1_25 */
 173                         AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_a10.gpio1_26 */
 174                         AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_a11.gpio1_27 */
 175                 >;
 176         };
 177
 178         volume_keys_s0: volume_keys_s0 {
 179                 pinctrl-single,pins = <
 180                         AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* spi0_sclk.gpio0_2 */
 181                         AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE7)       /* spi0_d0.gpio0_3 */
 182                 >;
 183         };
 184
 185         i2c0_pins: pinmux_i2c0_pins {
 186                 pinctrl-single,pins = <
 187                         AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)        /* i2c0_sda.i2c0_sda */
 188                         AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)        /* i2c0_scl.i2c0_scl */
 189                 >;
 190         };
 191
 192         i2c1_pins: pinmux_i2c1_pins {
 193                 pinctrl-single,pins = <
 194                         AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */
 195                         AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2)        /* spi0_cs0.i2c1_scl */
 196                 >;
 197         };
 198
 199         uart0_pins: pinmux_uart0_pins {
 200                 pinctrl-single,pins = <
 201                         AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
 202                         AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 203                 >;
 204         };
 205
 206         uart1_pins: pinmux_uart1_pins {
 207                 pinctrl-single,pins = <
 208                         AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)
 209                         AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 210                         AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
 211                         AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 212                 >;
 213         };
 214
 215         clkout2_pin: pinmux_clkout2_pin {
 216                 pinctrl-single,pins = <
 217                         AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3)     /* xdma_event_intr1.clkout2 */
 218                 >;
 219         };
 220
 221         nandflash_pins_s0: nandflash_pins_s0 {
 222                 pinctrl-single,pins = <
 223                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
 224                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
 225                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
 226                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
 227                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
 228                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
 229                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
 230                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
 231                         AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
 232                         AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7)        /* gpmc_wpn.gpio0_31 */
 233                         AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
 234                         AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
 235                         AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
 236                         AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
 237                         AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
 238                 >;
 239         };
 240
 241         ecap0_pins: backlight_pins {
 242                 pinctrl-single,pins = <
 243                         AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0)
 244                 >;
 245         };
 246
 247         cpsw_default: cpsw_default {
 248                 pinctrl-single,pins = <
 249                         /* Slave 1 */
 250                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2)   /* mii1_txen.rgmii1_tctl */
 251                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2)    /* mii1_rxdv.rgmii1_rctl */
 252                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd3.rgmii1_td3 */
 253                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd2.rgmii1_td2 */
 254                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd1.rgmii1_td1 */
 255                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd0.rgmii1_td0 */
 256                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2)  /* mii1_txclk.rgmii1_tclk */
 257                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2)   /* mii1_rxclk.rgmii1_rclk */
 258                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd3.rgmii1_rd3 */
 259                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd2.rgmii1_rd2 */
 260                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd1.rgmii1_rd1 */
 261                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd0.rgmii1_rd0 */
 262                 >;
 263         };
 264
 265         cpsw_sleep: cpsw_sleep {
 266                 pinctrl-single,pins = <
 267                         /* Slave 1 reset value */
 268                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
 269                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
 270                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
 271                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
 272                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
 273                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
 274                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
 275                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
 276                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
 277                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
 278                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
 279                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
 280                 >;
 281         };
 282
 283         davinci_mdio_default: davinci_mdio_default {
 284                 pinctrl-single,pins = <
 285                         /* MDIO */
 286                         AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
 287                         AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
 288                 >;
 289         };
 290
 291         davinci_mdio_sleep: davinci_mdio_sleep {
 292                 pinctrl-single,pins = <
 293                         /* MDIO reset value */
 294                         AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
 295                         AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
 296                 >;
 297         };
 298
 299         mmc1_pins: pinmux_mmc1_pins {
 300                 pinctrl-single,pins = <
 301                         AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7)               /* spi0_cs1.gpio0_6 */
 302                         AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
 303                         AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
 304                         AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
 305                         AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
 306                         AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
 307                         AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
 308                         AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4)           /* mcasp0_aclkr.mmc0_sdwp */
 309                 >;
 310         };
 311
 312         mmc3_pins: pinmux_mmc3_pins {
 313                 pinctrl-single,pins = <
 314                         AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
 315                         AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
 316                         AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
 317                         AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE3)       /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
 318                         AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3)       /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
 319                         AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3)        /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
 320                 >;
 321         };
 322
 323         wlan_pins: pinmux_wlan_pins {
 324                 pinctrl-single,pins = <
 325                         AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* gpmc_a0.gpio1_16 */
 326                         AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT, MUX_MODE7)          /* mcasp0_ahclkr.gpio3_17 */
 327                         AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE7)        /* mcasp0_ahclkx.gpio3_21 */
 328                 >;
 329         };
 330
 331         lcd_pins_s0: lcd_pins_s0 {
 332                 pinctrl-single,pins = <
 333                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1)              /* gpmc_ad8.lcd_data23 */
 334                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1)              /* gpmc_ad9.lcd_data22 */
 335                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1)             /* gpmc_ad10.lcd_data21 */
 336                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1)             /* gpmc_ad11.lcd_data20 */
 337                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1)             /* gpmc_ad12.lcd_data19 */
 338                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1)             /* gpmc_ad13.lcd_data18 */
 339                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1)             /* gpmc_ad14.lcd_data17 */
 340                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1)             /* gpmc_ad15.lcd_data16 */
 341                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
 342                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
 343                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
 344                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
 345                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
 346                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
 347                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
 348                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
 349                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
 350                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
 351                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
 352                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
 353                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
 354                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
 355                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
 356                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
 357                         AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
 358                         AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
 359                         AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
 360                         AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
 361                 >;
 362         };
 363
 364         mcasp1_pins: mcasp1_pins {
 365                 pinctrl-single,pins = <
 366                         AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
 367                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
 368                         AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */
 369                         AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
 370                 >;
 371         };
 372
 373         mcasp1_pins_sleep: mcasp1_pins_sleep {
 374                 pinctrl-single,pins = <
 375                         AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
 376                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
 377                         AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7)
 378                         AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
 379                 >;
 380         };
 381
 382         dcan1_pins_default: dcan1_pins_default {
 383                 pinctrl-single,pins = <
 384                         AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.d_can1_tx */
 385                         AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart0_rtsn.d_can1_rx */
 386                 >;
 387         };
 388 };
 389
 390 &uart0 {
 391         pinctrl-names = "default";
 392         pinctrl-0 = <&uart0_pins>;
 393
 394         status = "okay";
 395 };
 396
 397 &uart1 {
 398         pinctrl-names = "default";
 399         pinctrl-0 = <&uart1_pins>;
 400
 401         status = "okay";
 402 };
 403
 404 &i2c0 {
 405         pinctrl-names = "default";
 406         pinctrl-0 = <&i2c0_pins>;
 407
 408         status = "okay";
 409         clock-frequency = <400000>;
 410
 411         tps: tps@2d {
 412                 reg = <0x2d>;
 413         };
 414 };
 415
 416 &usb1 {
 417         dr_mode = "host";
 418 };
 419
 420 &i2c1 {
 421         pinctrl-names = "default";
 422         pinctrl-0 = <&i2c1_pins>;
 423
 424         status = "okay";
 425         clock-frequency = <100000>;
 426
 427         lis331dlh: lis331dlh@18 {
 428                 compatible = "st,lis331dlh", "st,lis3lv02d";
 429                 reg = <0x18>;
 430                 Vdd-supply = <&lis3_reg>;
 431                 Vdd_IO-supply = <&lis3_reg>;
 432
 433                 st,click-single-x;
 434                 st,click-single-y;
 435                 st,click-single-z;
 436                 st,click-thresh-x = <10>;
 437                 st,click-thresh-y = <10>;
 438                 st,click-thresh-z = <10>;
 439                 st,irq1-click;
 440                 st,irq2-click;
 441                 st,wakeup-x-lo;
 442                 st,wakeup-x-hi;
 443                 st,wakeup-y-lo;
 444                 st,wakeup-y-hi;
 445                 st,wakeup-z-lo;
 446                 st,wakeup-z-hi;
 447                 st,min-limit-x = <120>;
 448                 st,min-limit-y = <120>;
 449                 st,min-limit-z = <140>;
 450                 st,max-limit-x = <550>;
 451                 st,max-limit-y = <550>;
 452                 st,max-limit-z = <750>;
 453         };
 454
 455         tsl2550: tsl2550@39 {
 456                 compatible = "taos,tsl2550";
 457                 reg = <0x39>;
 458         };
 459
 460         tmp275: tmp275@48 {
 461                 compatible = "ti,tmp275";
 462                 reg = <0x48>;
 463         };
 464
 465         tlv320aic3106: tlv320aic3106@1b {
 466                 #sound-dai-cells = <0>;
 467                 compatible = "ti,tlv320aic3106";
 468                 reg = <0x1b>;
 469                 status = "okay";
 470
 471                 /* Regulators */
 472                 AVDD-supply = <&v3_3d_reg>;
 473                 IOVDD-supply = <&v3_3d_reg>;
 474                 DRVDD-supply = <&v3_3d_reg>;
 475                 DVDD-supply = <&v1_8d_reg>;
 476         };
 477 };
 478
 479 &lcdc {
 480         status = "okay";
 481
 482         blue-and-red-wiring = "crossed";
 483
 484         port {
 485                 lcdc_0: endpoint@0 {
 486                         remote-endpoint = <&panel_0>;
 487                 };
 488         };
 489 };
 490
 491 &elm {
 492         status = "okay";
 493 };
 494
 495 &epwmss0 {
 496         status = "okay";
 497
 498         ecap0: ecap@100 {
 499                 status = "okay";
 500                 pinctrl-names = "default";
 501                 pinctrl-0 = <&ecap0_pins>;
 502         };
 503 };
 504
 505 &gpmc {
 506         status = "okay";
 507         pinctrl-names = "default";
 508         pinctrl-0 = <&nandflash_pins_s0>;
 509         ranges = <0 0 0x08000000 0x1000000>;    /* CS0: 16MB for NAND */
 510         nand@0,0 {
 511                 compatible = "ti,omap2-nand";
 512                 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
 513                 interrupt-parent = <&gpmc>;
 514                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 515                              <1 IRQ_TYPE_NONE>; /* termcount */
 516                 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
 517                 ti,nand-xfer-type = "prefetch-dma";
 518                 ti,nand-ecc-opt = "bch8";
 519                 ti,elm-id = <&elm>;
 520                 nand-bus-width = <8>;
 521                 gpmc,device-width = <1>;
 522                 gpmc,sync-clk-ps = <0>;
 523                 gpmc,cs-on-ns = <0>;
 524                 gpmc,cs-rd-off-ns = <44>;
 525                 gpmc,cs-wr-off-ns = <44>;
 526                 gpmc,adv-on-ns = <6>;
 527                 gpmc,adv-rd-off-ns = <34>;
 528                 gpmc,adv-wr-off-ns = <44>;
 529                 gpmc,we-on-ns = <0>;
 530                 gpmc,we-off-ns = <40>;
 531                 gpmc,oe-on-ns = <0>;
 532                 gpmc,oe-off-ns = <54>;
 533                 gpmc,access-ns = <64>;
 534                 gpmc,rd-cycle-ns = <82>;
 535                 gpmc,wr-cycle-ns = <82>;
 536                 gpmc,bus-turnaround-ns = <0>;
 537                 gpmc,cycle2cycle-delay-ns = <0>;
 538                 gpmc,clk-activation-ns = <0>;
 539                 gpmc,wr-access-ns = <40>;
 540                 gpmc,wr-data-mux-bus-ns = <0>;
 541                 /* MTD partition table */
 542                 /* All SPL-* partitions are sized to minimal length
 543                  * which can be independently programmable. For
 544                  * NAND flash this is equal to size of erase-block */
 545                 #address-cells = <1>;
 546                 #size-cells = <1>;
 547                 partition@0 {
 548                         label = "NAND.SPL";
 549                         reg = <0x00000000 0x000020000>;
 550                 };
 551                 partition@1 {
 552                         label = "NAND.SPL.backup1";
 553                         reg = <0x00020000 0x00020000>;
 554                 };
 555                 partition@2 {
 556                         label = "NAND.SPL.backup2";
 557                         reg = <0x00040000 0x00020000>;
 558                 };
 559                 partition@3 {
 560                         label = "NAND.SPL.backup3";
 561                         reg = <0x00060000 0x00020000>;
 562                 };
 563                 partition@4 {
 564                         label = "NAND.u-boot-spl-os";
 565                         reg = <0x00080000 0x00040000>;
 566                 };
 567                 partition@5 {
 568                         label = "NAND.u-boot";
 569                         reg = <0x000C0000 0x00100000>;
 570                 };
 571                 partition@6 {
 572                         label = "NAND.u-boot-env";
 573                         reg = <0x001C0000 0x00020000>;
 574                 };
 575                 partition@7 {
 576                         label = "NAND.u-boot-env.backup1";
 577                         reg = <0x001E0000 0x00020000>;
 578                 };
 579                 partition@8 {
 580                         label = "NAND.kernel";
 581                         reg = <0x00200000 0x00800000>;
 582                 };
 583                 partition@9 {
 584                         label = "NAND.file-system";
 585                         reg = <0x00A00000 0x0F600000>;
 586                 };
 587         };
 588 };
 589
 590 #include "tps65910.dtsi"
 591
 592 &mcasp1 {
 593         #sound-dai-cells = <0>;
 594         pinctrl-names = "default", "sleep";
 595         pinctrl-0 = <&mcasp1_pins>;
 596         pinctrl-1 = <&mcasp1_pins_sleep>;
 597
 598         status = "okay";
 599
 600         op-mode = <0>;          /* MCASP_IIS_MODE */
 601         tdm-slots = <2>;
 602         /* 4 serializers */
 603         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 604                 0 0 1 2
 605         >;
 606         tx-num-evt = <32>;
 607         rx-num-evt = <32>;
 608 };
 609
 610 &tps {
 611         vcc1-supply = <&vbat>;
 612         vcc2-supply = <&vbat>;
 613         vcc3-supply = <&vbat>;
 614         vcc4-supply = <&vbat>;
 615         vcc5-supply = <&vbat>;
 616         vcc6-supply = <&vbat>;
 617         vcc7-supply = <&vbat>;
 618         vccio-supply = <&vbat>;
 619
 620         regulators {
 621                 vrtc_reg: regulator@0 {
 622                         regulator-always-on;
 623                 };
 624
 625                 vio_reg: regulator@1 {
 626                         regulator-always-on;
 627                 };
 628
 629                 vdd1_reg: regulator@2 {
 630                         /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
 631                         regulator-name = "vdd_mpu";
 632                         regulator-min-microvolt = <912500>;
 633                         regulator-max-microvolt = <1351500>;
 634                         regulator-boot-on;
 635                         regulator-always-on;
 636                 };
 637
 638                 vdd2_reg: regulator@3 {
 639                         /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
 640                         regulator-name = "vdd_core";
 641                         regulator-min-microvolt = <912500>;
 642                         regulator-max-microvolt = <1150000>;
 643                         regulator-boot-on;
 644                         regulator-always-on;
 645                 };
 646
 647                 vdd3_reg: regulator@4 {
 648                         regulator-always-on;
 649                 };
 650
 651                 vdig1_reg: regulator@5 {
 652                         regulator-always-on;
 653                 };
 654
 655                 vdig2_reg: regulator@6 {
 656                         regulator-always-on;
 657                 };
 658
 659                 vpll_reg: regulator@7 {
 660                         regulator-always-on;
 661                 };
 662
 663                 vdac_reg: regulator@8 {
 664                         regulator-always-on;
 665                 };
 666
 667                 vaux1_reg: regulator@9 {
 668                         regulator-always-on;
 669                 };
 670
 671                 vaux2_reg: regulator@10 {
 672                         regulator-always-on;
 673                 };
 674
 675                 vaux33_reg: regulator@11 {
 676                         regulator-always-on;
 677                 };
 678
 679                 vmmc_reg: regulator@12 {
 680                         regulator-min-microvolt = <1800000>;
 681                         regulator-max-microvolt = <3300000>;
 682                         regulator-always-on;
 683                 };
 684         };
 685 };
 686
 687 &mac {
 688         pinctrl-names = "default", "sleep";
 689         pinctrl-0 = <&cpsw_default>;
 690         pinctrl-1 = <&cpsw_sleep>;
 691         status = "okay";
 692         slaves = <1>;
 693 };
 694
 695 &davinci_mdio {
 696         pinctrl-names = "default", "sleep";
 697         pinctrl-0 = <&davinci_mdio_default>;
 698         pinctrl-1 = <&davinci_mdio_sleep>;
 699         status = "okay";
 700
 701         ethphy0: ethernet-phy@0 {
 702                 reg = <0>;
 703         };
 704 };
 705
 706 &cpsw_emac0 {
 707         phy-handle = <&ethphy0>;
 708         phy-mode = "rgmii-id";
 709 };
 710
 711 &tscadc {
 712         status = "okay";
 713         tsc {
 714                 ti,wires = <4>;
 715                 ti,x-plate-resistance = <200>;
 716                 ti,coordinate-readouts = <5>;
 717                 ti,wire-config = <0x00 0x11 0x22 0x33>;
 718                 ti,charge-delay = <0x400>;
 719         };
 720
 721         adc {
 722                 ti,adc-channels = <4 5 6 7>;
 723         };
 724 };
 725
 726 &mmc1 {
 727         status = "okay";
 728         vmmc-supply = <&vmmc_reg>;
 729         bus-width = <4>;
 730         pinctrl-names = "default";
 731         pinctrl-0 = <&mmc1_pins>;
 732         cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
 733 };
 734
 735 &mmc3 {
 736         /* these are on the crossbar and are outlined in the
 737            xbar-event-map element */
 738         dmas = <&edma_xbar 12 0 1
 739                 &edma_xbar 13 0 2>;
 740         dma-names = "tx", "rx";
 741         status = "okay";
 742         vmmc-supply = <&wlan_en_reg>;
 743         bus-width = <4>;
 744         pinctrl-names = "default";
 745         pinctrl-0 = <&mmc3_pins &wlan_pins>;
 746         non-removable;
 747         cap-power-off-card;
 748         keep-power-in-suspend;
 749
 750         #address-cells = <1>;
 751         #size-cells = <0>;
 752         wlcore: wlcore@0 {
 753                 compatible = "ti,wl1835";
 754                 reg = <2>;
 755                 interrupt-parent = <&gpio3>;
 756                 interrupts = <17 IRQ_TYPE_EDGE_RISING>;
 757         };
 758 };
 759
 760 &sham {
 761         status = "okay";
 762 };
 763
 764 &aes {
 765         status = "okay";
 766 };
 767
 768 &dcan1 {
 769         status = "disabled";    /* Enable only if Profile 1 is selected */
 770         pinctrl-names = "default";
 771         pinctrl-0 = <&dcan1_pins_default>;
 772 };
 773
 774 &rtc {
 775         clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
 776         clock-names = "ext-clk", "int-clk";
 777 };