arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2020 AMD Inc.
   3 // Author: Supreeth Venkatesh <supreeth.venkatesh@amd.com>
   4 /dts-v1/;
   5
   6 #include "aspeed-g5.dtsi"
   7 #include <dt-bindings/gpio/aspeed-gpio.h>
   8
   9 / {
  10         model = "AMD EthanolX BMC";
  11         compatible = "amd,ethanolx-bmc", "aspeed,ast2500";
  12
  13         memory@80000000 {
  14                 reg = <0x80000000 0x20000000>;
  15         };
  16
  17         reserved-memory {
  18                 #address-cells = <1>;
  19                 #size-cells = <1>;
  20                 ranges;
  21
  22                 video_engine_memory: jpegbuffer {
  23                         size = <0x02000000>;    /* 32M */
  24                         alignment = <0x01000000>;
  25                         compatible = "shared-dma-pool";
  26                         reusable;
  27                 };
  28         };
  29
  30
  31         aliases {
  32                 serial0 = &uart1;
  33                 serial4 = &uart5;
  34         };
  35         chosen {
  36                 stdout-path = &uart5;
  37                 bootargs = "console=ttyS4,115200 earlyprintk";
  38         };
  39         leds {
  40                 compatible = "gpio-leds";
  41
  42                 fault {
  43                         gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>;
  44                 };
  45
  46                 identify {
  47                         gpios = <&gpio ASPEED_GPIO(A, 3) GPIO_ACTIVE_LOW>;
  48                 };
  49         };
  50         iio-hwmon {
  51                 compatible = "iio-hwmon";
  52                 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>;
  53         };
  54 };
  55
  56 &fmc {
  57         status = "okay";
  58         flash@0 {
  59                 status = "okay";
  60                 m25p,fast-read;
  61                 #include "openbmc-flash-layout.dtsi"
  62         };
  63 };
  64
  65
  66 &mac0 {
  67         status = "okay";
  68
  69         pinctrl-names = "default";
  70         pinctrl-0 = <&pinctrl_rmii1_default>;
  71         clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
  72                  <&syscon ASPEED_CLK_MAC1RCLK>;
  73         clock-names = "MACCLK", "RCLK";
  74 };
  75
  76 &uart1 {
  77         //Host Console
  78         status = "okay";
  79         pinctrl-names = "default";
  80         pinctrl-0 = <&pinctrl_txd1_default
  81                      &pinctrl_rxd1_default>;
  82 };
  83
  84 &uart5 {
  85         //BMC Console
  86         status = "okay";
  87 };
  88
  89 &adc {
  90         status = "okay";
  91
  92         pinctrl-names = "default";
  93         pinctrl-0 = <&pinctrl_adc0_default
  94                      &pinctrl_adc1_default
  95                      &pinctrl_adc2_default
  96                      &pinctrl_adc3_default
  97                      &pinctrl_adc4_default>;
  98 };
  99
 100 &gpio {
 101         status = "okay";
 102         gpio-line-names =
 103         /*A0-A7*/       "","","FAULT_LED","CHASSIS_ID_LED","","","","",
 104         /*B0-B7*/       "","","","","","","","",
 105         /*C0-C7*/       "CHASSIS_ID_BTN","INTRUDER","AC_LOSS","","","","","",
 106         /*D0-D7*/       "HDT_DBREQ","LOCAL_SPI_ROM_SEL","FPGA_SPI_ROM_SEL","JTAG_MUX_S",
 107                         "JTAG_MUX_OE","HDT_SEL","ASERT_WARM_RST_BTN","FPGA_RSVD",
 108         /*E0-E7*/       "","","MON_P0_PWR_BTN","MON_P0_RST_BTN","MON_P0_NMI_BTN",
 109                         "MON_P0_PWR_GOOD","MON_PWROK","MON_RESET",
 110         /*F0-F7*/       "MON_P0_PROCHOT","MON_P1_PROCHOT","MON_P0_THERMTRIP",
 111                         "MON_P1_THERMTRIP","P0_PRESENT","P1_PRESENT","MON_ATX_PWR_OK","",
 112         /*G0-G7*/       "BRD_REV_ID_3","BRD_REV_ID_2","BRD_REV_ID_1","BRD_REV_ID_0",
 113                         "P0_APML_ALERT","P1_APML_ALERT","FPGA ALERT","",
 114         /*H0-H7*/       "BRD_ID_0","BRD_ID_1","BRD_ID_2","BRD_ID_3",
 115                         "PCIE_DISCONNECTED","USB_DISCONNECTED","SPARE_0","SPARE_1",
 116         /*I0-I7*/       "","","","","","","","",
 117         /*J0-J7*/       "","","","","","","","",
 118         /*K0-K7*/       "","","","","","","","",
 119         /*L0-L7*/       "","","","","","","","",
 120         /*M0-M7*/       "ASSERT_PWR_BTN","ASSERT_RST_BTN","ASSERT_NMI_BTN",
 121                         "ASSERT_LOCAL_LOCK","ASSERT_P0_PROCHOT","ASSERT_P1_PROCHOT",
 122                         "ASSERT_CLR_CMOS","ASSERT_BMC_READY",
 123         /*N0-N7*/       "","","","","","","","",
 124         /*O0-O7*/       "","","","","","","","",
 125         /*P0-P7*/       "P0_VDD_CORE_RUN_VRHOT","P0_VDD_SOC_RUN_VRHOT",
 126                         "P0_VDD_MEM_ABCD_SUS_VRHOT","P0_VDD_MEM_EFGH_SUS_VRHOT",
 127                         "P1_VDD_CORE_RUN_VRHOT","P1_VDD_SOC_RUN_VRHOT",
 128                         "P1_VDD_MEM_ABCD_SUS_VRHOT","P1_VDD_MEM_EFGH_SUS_VRHOT",
 129         /*Q0-Q7*/       "","","","","","","","",
 130         /*R0-R7*/       "","","","","","","","",
 131         /*S0-S7*/       "","","","","","","","",
 132         /*T0-T7*/       "","","","","","","","",
 133         /*U0-U7*/       "","","","","","","","",
 134         /*V0-V7*/       "","","","","","","","",
 135         /*W0-W7*/       "","","","","","","","",
 136         /*X0-X7*/       "","","","","","","","",
 137         /*Y0-Y7*/       "","","","","","","","",
 138         /*Z0-Z7*/       "","","","","","","","",
 139         /*AA0-AA7*/     "","SENSOR THERM","","","","","","",
 140         /*AB0-AB7*/     "","","","","","","","",
 141         /*AC0-AC7*/     "","","","","","","","";
 142 };
 143
 144 //APML for P0
 145 &i2c0 {
 146         status = "okay";
 147 };
 148
 149 //APML for P1
 150 &i2c1 {
 151         status = "okay";
 152 };
 153
 154 // Thermal Sensors
 155 &i2c7 {
 156         status = "okay";
 157
 158         lm75a@48 {
 159                 compatible = "national,lm75a";
 160                 reg = <0x48>;
 161         };
 162
 163         lm75a@49 {
 164                 compatible = "national,lm75a";
 165                 reg = <0x49>;
 166         };
 167
 168         lm75a@4a {
 169                 compatible = "national,lm75a";
 170                 reg = <0x4a>;
 171         };
 172
 173         lm75a@4b {
 174                 compatible = "national,lm75a";
 175                 reg = <0x4b>;
 176         };
 177
 178         lm75a@4c {
 179                 compatible = "national,lm75a";
 180                 reg = <0x4c>;
 181         };
 182
 183         lm75a@4d {
 184                 compatible = "national,lm75a";
 185                 reg = <0x4d>;
 186         };
 187
 188         lm75a@4e {
 189                 compatible = "national,lm75a";
 190                 reg = <0x4e>;
 191         };
 192
 193         lm75a@4f {
 194                 compatible = "national,lm75a";
 195                 reg = <0x4f>;
 196         };
 197 };
 198
 199 &kcs1 {
 200         status = "okay";
 201         aspeed,lpc-io-reg = <0x60>;
 202 };
 203
 204 &kcs2 {
 205         status = "okay";
 206         aspeed,lpc-io-reg = <0x62>;
 207 };
 208
 209 &kcs3 {
 210         status = "okay";
 211         aspeed,lpc-io-reg = <0xCA2>;
 212 };
 213
 214 &kcs4 {
 215         status = "okay";
 216         aspeed,lpc-io-reg = <0x97DE>;
 217 };
 218
 219 &lpc_snoop {
 220         status = "okay";
 221         snoop-ports = <0x80>;
 222 };
 223
 224 &lpc_ctrl {
 225         //Enable lpc clock
 226         status = "okay";
 227 };
 228
 229 &pwm_tacho {
 230         status = "okay";
 231         pinctrl-names = "default";
 232         pinctrl-0 = <&pinctrl_pwm0_default
 233         &pinctrl_pwm1_default
 234         &pinctrl_pwm2_default
 235         &pinctrl_pwm3_default
 236         &pinctrl_pwm4_default
 237         &pinctrl_pwm5_default
 238         &pinctrl_pwm6_default
 239         &pinctrl_pwm7_default>;
 240
 241         fan@0 {
 242                 reg = <0x00>;
 243                 aspeed,fan-tach-ch = /bits/ 8 <0x00>;
 244         };
 245
 246         fan@1 {
 247                 reg = <0x01>;
 248                 aspeed,fan-tach-ch = /bits/ 8 <0x01>;
 249         };
 250
 251         fan@2 {
 252                 reg = <0x02>;
 253                 aspeed,fan-tach-ch = /bits/ 8 <0x02>;
 254         };
 255
 256         fan@3 {
 257                 reg = <0x03>;
 258                 aspeed,fan-tach-ch = /bits/ 8 <0x03>;
 259         };
 260
 261         fan@4 {
 262                 reg = <0x04>;
 263                 aspeed,fan-tach-ch = /bits/ 8 <0x04>;
 264         };
 265
 266         fan@5 {
 267                 reg = <0x05>;
 268                 aspeed,fan-tach-ch = /bits/ 8 <0x05>;
 269         };
 270
 271         fan@6 {
 272                 reg = <0x06>;
 273                 aspeed,fan-tach-ch = /bits/ 8 <0x06>;
 274         };
 275
 276         fan@7 {
 277                 reg = <0x07>;
 278                 aspeed,fan-tach-ch = /bits/ 8 <0x07>;
 279         };
 280 };
 281
 282 &video {
 283         status = "okay";
 284         memory-region = <&video_engine_memory>;
 285 };
 286
 287 &vhub {
 288         status = "okay";
 289 };
 290