arch/arm/boot/dts/dra72-evm-revc.dts

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
   4  */
   5 #include "dra72-evm-common.dtsi"
   6 #include "dra72x-mmc-iodelay.dtsi"
   7 #include <dt-bindings/net/ti-dp83867.h>
   8
   9 / {
  10         model = "TI DRA722 Rev C EVM";
  11
  12         memory@0 {
  13                 device_type = "memory";
  14                 reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */
  15         };
  16
  17         reserved-memory {
  18                 #address-cells = <2>;
  19                 #size-cells = <2>;
  20                 ranges;
  21
  22                 ipu2_cma_pool: ipu2_cma@95800000 {
  23                         compatible = "shared-dma-pool";
  24                         reg = <0x0 0x95800000 0x0 0x3800000>;
  25                         reusable;
  26                         status = "okay";
  27                 };
  28
  29                 dsp1_cma_pool: dsp1_cma@99000000 {
  30                         compatible = "shared-dma-pool";
  31                         reg = <0x0 0x99000000 0x0 0x4000000>;
  32                         reusable;
  33                         status = "okay";
  34                 };
  35
  36                 ipu1_cma_pool: ipu1_cma@9d000000 {
  37                         compatible = "shared-dma-pool";
  38                         reg = <0x0 0x9d000000 0x0 0x2000000>;
  39                         reusable;
  40                         status = "okay";
  41                 };
  42         };
  43
  44         evm_1v8_sw: fixedregulator-evm_1v8 {
  45                 compatible = "regulator-fixed";
  46                 regulator-name = "evm_1v8";
  47                 regulator-min-microvolt = <1800000>;
  48                 regulator-max-microvolt = <1800000>;
  49                 vin-supply = <&smps4_reg>;
  50                 regulator-always-on;
  51                 regulator-boot-on;
  52         };
  53 };
  54
  55 &i2c1 {
  56         tps65917: tps65917@58 {
  57                 reg = <0x58>;
  58
  59                 interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;  /* IRQ_SYS_1N */
  60         };
  61 };
  62
  63 #include "dra72-evm-tps65917.dtsi"
  64
  65 &ldo2_reg {
  66         /* LDO2_OUT --> VDDA_1V8_PHY2 */
  67         regulator-always-on;
  68         regulator-boot-on;
  69 };
  70
  71 &hdmi {
  72         vdda-supply = <&ldo2_reg>;
  73 };
  74
  75 &pcf_gpio_21 {
  76         interrupt-parent = <&gpio3>;
  77         interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
  78 };
  79
  80 &mac_sw {
  81         mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>,
  82                      <&pcf_hdmi 9 GPIO_ACTIVE_LOW>,     /* P11 */
  83                      <&pcf_hdmi 10 GPIO_ACTIVE_LOW>;    /* P12 */
  84         status = "okay";
  85 };
  86
  87 &cpsw_port1 {
  88         phy-handle = <&dp83867_0>;
  89         phy-mode = "rgmii-id";
  90         ti,dual-emac-pvid = <1>;
  91 };
  92
  93 &cpsw_port2 {
  94         phy-handle = <&dp83867_1>;
  95         phy-mode = "rgmii-id";
  96         ti,dual-emac-pvid = <2>;
  97 };
  98
  99 &davinci_mdio_sw {
 100         dp83867_0: ethernet-phy@2 {
 101                 reg = <2>;
 102                 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
 103                 ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
 104                 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
 105                 ti,min-output-impedance;
 106                 interrupt-parent = <&gpio6>;
 107                 interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
 108                 ti,dp83867-rxctrl-strap-quirk;
 109         };
 110
 111         dp83867_1: ethernet-phy@3 {
 112                 reg = <3>;
 113                 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
 114                 ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
 115                 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
 116                 ti,min-output-impedance;
 117                 interrupt-parent = <&gpio6>;
 118                 interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
 119                 ti,dp83867-rxctrl-strap-quirk;
 120         };
 121 };
 122
 123 &mmc1 {
 124         pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
 125         pinctrl-0 = <&mmc1_pins_default>;
 126         pinctrl-1 = <&mmc1_pins_hs>;
 127         pinctrl-2 = <&mmc1_pins_sdr12>;
 128         pinctrl-3 = <&mmc1_pins_sdr25>;
 129         pinctrl-4 = <&mmc1_pins_sdr50>;
 130         pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
 131         pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
 132         vqmmc-supply = <&ldo1_reg>;
 133 };
 134
 135 &mmc2 {
 136         pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
 137         pinctrl-0 = <&mmc2_pins_default>;
 138         pinctrl-1 = <&mmc2_pins_hs>;
 139         pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
 140         pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>;
 141         vmmc-supply = <&evm_1v8_sw>;
 142 };
 143
 144 &ipu2 {
 145         status = "okay";
 146         memory-region = <&ipu2_cma_pool>;
 147 };
 148
 149 &ipu1 {
 150         status = "okay";
 151         memory-region = <&ipu1_cma_pool>;
 152 };
 153
 154 &dsp1 {
 155         status = "okay";
 156         memory-region = <&dsp1_cma_pool>;
 157 };