arch/arm/boot/dts/dra7xx-clocks.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Device Tree Source for DRA7xx clock data
   4  *
   5  * Copyright (C) 2013 Texas Instruments, Inc.
   6  */
   7 &cm_core_aon_clocks {
   8         atl_clkin0_ck: atl_clkin0_ck {
   9                 #clock-cells = <0>;
  10                 compatible = "ti,dra7-atl-clock";
  11                 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
  12         };
  13
  14         atl_clkin1_ck: atl_clkin1_ck {
  15                 #clock-cells = <0>;
  16                 compatible = "ti,dra7-atl-clock";
  17                 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
  18         };
  19
  20         atl_clkin2_ck: atl_clkin2_ck {
  21                 #clock-cells = <0>;
  22                 compatible = "ti,dra7-atl-clock";
  23                 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
  24         };
  25
  26         atl_clkin3_ck: atl_clkin3_ck {
  27                 #clock-cells = <0>;
  28                 compatible = "ti,dra7-atl-clock";
  29                 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
  30         };
  31
  32         hdmi_clkin_ck: hdmi_clkin_ck {
  33                 #clock-cells = <0>;
  34                 compatible = "fixed-clock";
  35                 clock-frequency = <0>;
  36         };
  37
  38         mlb_clkin_ck: mlb_clkin_ck {
  39                 #clock-cells = <0>;
  40                 compatible = "fixed-clock";
  41                 clock-frequency = <0>;
  42         };
  43
  44         mlbp_clkin_ck: mlbp_clkin_ck {
  45                 #clock-cells = <0>;
  46                 compatible = "fixed-clock";
  47                 clock-frequency = <0>;
  48         };
  49
  50         pciesref_acs_clk_ck: pciesref_acs_clk_ck {
  51                 #clock-cells = <0>;
  52                 compatible = "fixed-clock";
  53                 clock-frequency = <100000000>;
  54         };
  55
  56         ref_clkin0_ck: ref_clkin0_ck {
  57                 #clock-cells = <0>;
  58                 compatible = "fixed-clock";
  59                 clock-frequency = <0>;
  60         };
  61
  62         ref_clkin1_ck: ref_clkin1_ck {
  63                 #clock-cells = <0>;
  64                 compatible = "fixed-clock";
  65                 clock-frequency = <0>;
  66         };
  67
  68         ref_clkin2_ck: ref_clkin2_ck {
  69                 #clock-cells = <0>;
  70                 compatible = "fixed-clock";
  71                 clock-frequency = <0>;
  72         };
  73
  74         ref_clkin3_ck: ref_clkin3_ck {
  75                 #clock-cells = <0>;
  76                 compatible = "fixed-clock";
  77                 clock-frequency = <0>;
  78         };
  79
  80         rmii_clk_ck: rmii_clk_ck {
  81                 #clock-cells = <0>;
  82                 compatible = "fixed-clock";
  83                 clock-frequency = <0>;
  84         };
  85
  86         sdvenc_clkin_ck: sdvenc_clkin_ck {
  87                 #clock-cells = <0>;
  88                 compatible = "fixed-clock";
  89                 clock-frequency = <0>;
  90         };
  91
  92         secure_32k_clk_src_ck: secure_32k_clk_src_ck {
  93                 #clock-cells = <0>;
  94                 compatible = "fixed-clock";
  95                 clock-frequency = <32768>;
  96         };
  97
  98         sys_clk32_crystal_ck: sys_clk32_crystal_ck {
  99                 #clock-cells = <0>;
 100                 compatible = "fixed-clock";
 101                 clock-frequency = <32768>;
 102         };
 103
 104         sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
 105                 #clock-cells = <0>;
 106                 compatible = "fixed-factor-clock";
 107                 clocks = <&sys_clkin1>;
 108                 clock-mult = <1>;
 109                 clock-div = <610>;
 110         };
 111
 112         virt_12000000_ck: virt_12000000_ck {
 113                 #clock-cells = <0>;
 114                 compatible = "fixed-clock";
 115                 clock-frequency = <12000000>;
 116         };
 117
 118         virt_13000000_ck: virt_13000000_ck {
 119                 #clock-cells = <0>;
 120                 compatible = "fixed-clock";
 121                 clock-frequency = <13000000>;
 122         };
 123
 124         virt_16800000_ck: virt_16800000_ck {
 125                 #clock-cells = <0>;
 126                 compatible = "fixed-clock";
 127                 clock-frequency = <16800000>;
 128         };
 129
 130         virt_19200000_ck: virt_19200000_ck {
 131                 #clock-cells = <0>;
 132                 compatible = "fixed-clock";
 133                 clock-frequency = <19200000>;
 134         };
 135
 136         virt_20000000_ck: virt_20000000_ck {
 137                 #clock-cells = <0>;
 138                 compatible = "fixed-clock";
 139                 clock-frequency = <20000000>;
 140         };
 141
 142         virt_26000000_ck: virt_26000000_ck {
 143                 #clock-cells = <0>;
 144                 compatible = "fixed-clock";
 145                 clock-frequency = <26000000>;
 146         };
 147
 148         virt_27000000_ck: virt_27000000_ck {
 149                 #clock-cells = <0>;
 150                 compatible = "fixed-clock";
 151                 clock-frequency = <27000000>;
 152         };
 153
 154         virt_38400000_ck: virt_38400000_ck {
 155                 #clock-cells = <0>;
 156                 compatible = "fixed-clock";
 157                 clock-frequency = <38400000>;
 158         };
 159
 160         sys_clkin2: sys_clkin2 {
 161                 #clock-cells = <0>;
 162                 compatible = "fixed-clock";
 163                 clock-frequency = <22579200>;
 164         };
 165
 166         usb_otg_clkin_ck: usb_otg_clkin_ck {
 167                 #clock-cells = <0>;
 168                 compatible = "fixed-clock";
 169                 clock-frequency = <0>;
 170         };
 171
 172         video1_clkin_ck: video1_clkin_ck {
 173                 #clock-cells = <0>;
 174                 compatible = "fixed-clock";
 175                 clock-frequency = <0>;
 176         };
 177
 178         video1_m2_clkin_ck: video1_m2_clkin_ck {
 179                 #clock-cells = <0>;
 180                 compatible = "fixed-clock";
 181                 clock-frequency = <0>;
 182         };
 183
 184         video2_clkin_ck: video2_clkin_ck {
 185                 #clock-cells = <0>;
 186                 compatible = "fixed-clock";
 187                 clock-frequency = <0>;
 188         };
 189
 190         video2_m2_clkin_ck: video2_m2_clkin_ck {
 191                 #clock-cells = <0>;
 192                 compatible = "fixed-clock";
 193                 clock-frequency = <0>;
 194         };
 195
 196         dpll_abe_ck: dpll_abe_ck@1e0 {
 197                 #clock-cells = <0>;
 198                 compatible = "ti,omap4-dpll-m4xen-clock";
 199                 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
 200                 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
 201         };
 202
 203         dpll_abe_x2_ck: dpll_abe_x2_ck {
 204                 #clock-cells = <0>;
 205                 compatible = "ti,omap4-dpll-x2-clock";
 206                 clocks = <&dpll_abe_ck>;
 207         };
 208
 209         dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
 210                 #clock-cells = <0>;
 211                 compatible = "ti,divider-clock";
 212                 clocks = <&dpll_abe_x2_ck>;
 213                 ti,max-div = <31>;
 214                 ti,autoidle-shift = <8>;
 215                 reg = <0x01f0>;
 216                 ti,index-starts-at-one;
 217                 ti,invert-autoidle-bit;
 218         };
 219
 220         abe_clk: abe_clk@108 {
 221                 #clock-cells = <0>;
 222                 compatible = "ti,divider-clock";
 223                 clocks = <&dpll_abe_m2x2_ck>;
 224                 ti,max-div = <4>;
 225                 reg = <0x0108>;
 226                 ti,index-power-of-two;
 227         };
 228
 229         dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
 230                 #clock-cells = <0>;
 231                 compatible = "ti,divider-clock";
 232                 clocks = <&dpll_abe_ck>;
 233                 ti,max-div = <31>;
 234                 ti,autoidle-shift = <8>;
 235                 reg = <0x01f0>;
 236                 ti,index-starts-at-one;
 237                 ti,invert-autoidle-bit;
 238         };
 239
 240         dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
 241                 #clock-cells = <0>;
 242                 compatible = "ti,divider-clock";
 243                 clocks = <&dpll_abe_x2_ck>;
 244                 ti,max-div = <31>;
 245                 ti,autoidle-shift = <8>;
 246                 reg = <0x01f4>;
 247                 ti,index-starts-at-one;
 248                 ti,invert-autoidle-bit;
 249         };
 250
 251         dpll_core_byp_mux: dpll_core_byp_mux@12c {
 252                 #clock-cells = <0>;
 253                 compatible = "ti,mux-clock";
 254                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 255                 ti,bit-shift = <23>;
 256                 reg = <0x012c>;
 257         };
 258
 259         dpll_core_ck: dpll_core_ck@120 {
 260                 #clock-cells = <0>;
 261                 compatible = "ti,omap4-dpll-core-clock";
 262                 clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
 263                 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
 264         };
 265
 266         dpll_core_x2_ck: dpll_core_x2_ck {
 267                 #clock-cells = <0>;
 268                 compatible = "ti,omap4-dpll-x2-clock";
 269                 clocks = <&dpll_core_ck>;
 270         };
 271
 272         dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
 273                 #clock-cells = <0>;
 274                 compatible = "ti,divider-clock";
 275                 clocks = <&dpll_core_x2_ck>;
 276                 ti,max-div = <63>;
 277                 ti,autoidle-shift = <8>;
 278                 reg = <0x013c>;
 279                 ti,index-starts-at-one;
 280                 ti,invert-autoidle-bit;
 281         };
 282
 283         mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
 284                 #clock-cells = <0>;
 285                 compatible = "fixed-factor-clock";
 286                 clocks = <&dpll_core_h12x2_ck>;
 287                 clock-mult = <1>;
 288                 clock-div = <1>;
 289         };
 290
 291         dpll_mpu_ck: dpll_mpu_ck@160 {
 292                 #clock-cells = <0>;
 293                 compatible = "ti,omap5-mpu-dpll-clock";
 294                 clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
 295                 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
 296         };
 297
 298         dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
 299                 #clock-cells = <0>;
 300                 compatible = "ti,divider-clock";
 301                 clocks = <&dpll_mpu_ck>;
 302                 ti,max-div = <31>;
 303                 ti,autoidle-shift = <8>;
 304                 reg = <0x0170>;
 305                 ti,index-starts-at-one;
 306                 ti,invert-autoidle-bit;
 307         };
 308
 309         mpu_dclk_div: mpu_dclk_div {
 310                 #clock-cells = <0>;
 311                 compatible = "fixed-factor-clock";
 312                 clocks = <&dpll_mpu_m2_ck>;
 313                 clock-mult = <1>;
 314                 clock-div = <1>;
 315         };
 316
 317         dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
 318                 #clock-cells = <0>;
 319                 compatible = "fixed-factor-clock";
 320                 clocks = <&dpll_core_h12x2_ck>;
 321                 clock-mult = <1>;
 322                 clock-div = <1>;
 323         };
 324
 325         dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 {
 326                 #clock-cells = <0>;
 327                 compatible = "ti,mux-clock";
 328                 clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
 329                 ti,bit-shift = <23>;
 330                 reg = <0x0240>;
 331         };
 332
 333         dpll_dsp_ck: dpll_dsp_ck@234 {
 334                 #clock-cells = <0>;
 335                 compatible = "ti,omap4-dpll-clock";
 336                 clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
 337                 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
 338                 assigned-clocks = <&dpll_dsp_ck>;
 339                 assigned-clock-rates = <600000000>;
 340         };
 341
 342         dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
 343                 #clock-cells = <0>;
 344                 compatible = "ti,divider-clock";
 345                 clocks = <&dpll_dsp_ck>;
 346                 ti,max-div = <31>;
 347                 ti,autoidle-shift = <8>;
 348                 reg = <0x0244>;
 349                 ti,index-starts-at-one;
 350                 ti,invert-autoidle-bit;
 351                 assigned-clocks = <&dpll_dsp_m2_ck>;
 352                 assigned-clock-rates = <600000000>;
 353         };
 354
 355         iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
 356                 #clock-cells = <0>;
 357                 compatible = "fixed-factor-clock";
 358                 clocks = <&dpll_core_h12x2_ck>;
 359                 clock-mult = <1>;
 360                 clock-div = <1>;
 361         };
 362
 363         dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
 364                 #clock-cells = <0>;
 365                 compatible = "ti,mux-clock";
 366                 clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
 367                 ti,bit-shift = <23>;
 368                 reg = <0x01ac>;
 369         };
 370
 371         dpll_iva_ck: dpll_iva_ck@1a0 {
 372                 #clock-cells = <0>;
 373                 compatible = "ti,omap4-dpll-clock";
 374                 clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
 375                 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
 376                 assigned-clocks = <&dpll_iva_ck>;
 377                 assigned-clock-rates = <1165000000>;
 378         };
 379
 380         dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
 381                 #clock-cells = <0>;
 382                 compatible = "ti,divider-clock";
 383                 clocks = <&dpll_iva_ck>;
 384                 ti,max-div = <31>;
 385                 ti,autoidle-shift = <8>;
 386                 reg = <0x01b0>;
 387                 ti,index-starts-at-one;
 388                 ti,invert-autoidle-bit;
 389                 assigned-clocks = <&dpll_iva_m2_ck>;
 390                 assigned-clock-rates = <388333334>;
 391         };
 392
 393         iva_dclk: iva_dclk {
 394                 #clock-cells = <0>;
 395                 compatible = "fixed-factor-clock";
 396                 clocks = <&dpll_iva_m2_ck>;
 397                 clock-mult = <1>;
 398                 clock-div = <1>;
 399         };
 400
 401         dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 {
 402                 #clock-cells = <0>;
 403                 compatible = "ti,mux-clock";
 404                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 405                 ti,bit-shift = <23>;
 406                 reg = <0x02e4>;
 407         };
 408
 409         dpll_gpu_ck: dpll_gpu_ck@2d8 {
 410                 #clock-cells = <0>;
 411                 compatible = "ti,omap4-dpll-clock";
 412                 clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
 413                 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
 414                 assigned-clocks = <&dpll_gpu_ck>;
 415                 assigned-clock-rates = <1277000000>;
 416         };
 417
 418         dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
 419                 #clock-cells = <0>;
 420                 compatible = "ti,divider-clock";
 421                 clocks = <&dpll_gpu_ck>;
 422                 ti,max-div = <31>;
 423                 ti,autoidle-shift = <8>;
 424                 reg = <0x02e8>;
 425                 ti,index-starts-at-one;
 426                 ti,invert-autoidle-bit;
 427                 assigned-clocks = <&dpll_gpu_m2_ck>;
 428                 assigned-clock-rates = <425666667>;
 429         };
 430
 431         dpll_core_m2_ck: dpll_core_m2_ck@130 {
 432                 #clock-cells = <0>;
 433                 compatible = "ti,divider-clock";
 434                 clocks = <&dpll_core_ck>;
 435                 ti,max-div = <31>;
 436                 ti,autoidle-shift = <8>;
 437                 reg = <0x0130>;
 438                 ti,index-starts-at-one;
 439                 ti,invert-autoidle-bit;
 440         };
 441
 442         core_dpll_out_dclk_div: core_dpll_out_dclk_div {
 443                 #clock-cells = <0>;
 444                 compatible = "fixed-factor-clock";
 445                 clocks = <&dpll_core_m2_ck>;
 446                 clock-mult = <1>;
 447                 clock-div = <1>;
 448         };
 449
 450         dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c {
 451                 #clock-cells = <0>;
 452                 compatible = "ti,mux-clock";
 453                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 454                 ti,bit-shift = <23>;
 455                 reg = <0x021c>;
 456         };
 457
 458         dpll_ddr_ck: dpll_ddr_ck@210 {
 459                 #clock-cells = <0>;
 460                 compatible = "ti,omap4-dpll-clock";
 461                 clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
 462                 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
 463         };
 464
 465         dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 {
 466                 #clock-cells = <0>;
 467                 compatible = "ti,divider-clock";
 468                 clocks = <&dpll_ddr_ck>;
 469                 ti,max-div = <31>;
 470                 ti,autoidle-shift = <8>;
 471                 reg = <0x0220>;
 472                 ti,index-starts-at-one;
 473                 ti,invert-autoidle-bit;
 474         };
 475
 476         dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 {
 477                 #clock-cells = <0>;
 478                 compatible = "ti,mux-clock";
 479                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 480                 ti,bit-shift = <23>;
 481                 reg = <0x02b4>;
 482         };
 483
 484         dpll_gmac_ck: dpll_gmac_ck@2a8 {
 485                 #clock-cells = <0>;
 486                 compatible = "ti,omap4-dpll-clock";
 487                 clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
 488                 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
 489         };
 490
 491         dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 {
 492                 #clock-cells = <0>;
 493                 compatible = "ti,divider-clock";
 494                 clocks = <&dpll_gmac_ck>;
 495                 ti,max-div = <31>;
 496                 ti,autoidle-shift = <8>;
 497                 reg = <0x02b8>;
 498                 ti,index-starts-at-one;
 499                 ti,invert-autoidle-bit;
 500         };
 501
 502         video2_dclk_div: video2_dclk_div {
 503                 #clock-cells = <0>;
 504                 compatible = "fixed-factor-clock";
 505                 clocks = <&video2_m2_clkin_ck>;
 506                 clock-mult = <1>;
 507                 clock-div = <1>;
 508         };
 509
 510         video1_dclk_div: video1_dclk_div {
 511                 #clock-cells = <0>;
 512                 compatible = "fixed-factor-clock";
 513                 clocks = <&video1_m2_clkin_ck>;
 514                 clock-mult = <1>;
 515                 clock-div = <1>;
 516         };
 517
 518         hdmi_dclk_div: hdmi_dclk_div {
 519                 #clock-cells = <0>;
 520                 compatible = "fixed-factor-clock";
 521                 clocks = <&hdmi_clkin_ck>;
 522                 clock-mult = <1>;
 523                 clock-div = <1>;
 524         };
 525
 526         per_dpll_hs_clk_div: per_dpll_hs_clk_div {
 527                 #clock-cells = <0>;
 528                 compatible = "fixed-factor-clock";
 529                 clocks = <&dpll_abe_m3x2_ck>;
 530                 clock-mult = <1>;
 531                 clock-div = <2>;
 532         };
 533
 534         usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
 535                 #clock-cells = <0>;
 536                 compatible = "fixed-factor-clock";
 537                 clocks = <&dpll_abe_m3x2_ck>;
 538                 clock-mult = <1>;
 539                 clock-div = <3>;
 540         };
 541
 542         eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
 543                 #clock-cells = <0>;
 544                 compatible = "fixed-factor-clock";
 545                 clocks = <&dpll_core_h12x2_ck>;
 546                 clock-mult = <1>;
 547                 clock-div = <1>;
 548         };
 549
 550         dpll_eve_byp_mux: dpll_eve_byp_mux@290 {
 551                 #clock-cells = <0>;
 552                 compatible = "ti,mux-clock";
 553                 clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
 554                 ti,bit-shift = <23>;
 555                 reg = <0x0290>;
 556         };
 557
 558         dpll_eve_ck: dpll_eve_ck@284 {
 559                 #clock-cells = <0>;
 560                 compatible = "ti,omap4-dpll-clock";
 561                 clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
 562                 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
 563         };
 564
 565         dpll_eve_m2_ck: dpll_eve_m2_ck@294 {
 566                 #clock-cells = <0>;
 567                 compatible = "ti,divider-clock";
 568                 clocks = <&dpll_eve_ck>;
 569                 ti,max-div = <31>;
 570                 ti,autoidle-shift = <8>;
 571                 reg = <0x0294>;
 572                 ti,index-starts-at-one;
 573                 ti,invert-autoidle-bit;
 574         };
 575
 576         eve_dclk_div: eve_dclk_div {
 577                 #clock-cells = <0>;
 578                 compatible = "fixed-factor-clock";
 579                 clocks = <&dpll_eve_m2_ck>;
 580                 clock-mult = <1>;
 581                 clock-div = <1>;
 582         };
 583
 584         dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
 585                 #clock-cells = <0>;
 586                 compatible = "ti,divider-clock";
 587                 clocks = <&dpll_core_x2_ck>;
 588                 ti,max-div = <63>;
 589                 ti,autoidle-shift = <8>;
 590                 reg = <0x0140>;
 591                 ti,index-starts-at-one;
 592                 ti,invert-autoidle-bit;
 593         };
 594
 595         dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
 596                 #clock-cells = <0>;
 597                 compatible = "ti,divider-clock";
 598                 clocks = <&dpll_core_x2_ck>;
 599                 ti,max-div = <63>;
 600                 ti,autoidle-shift = <8>;
 601                 reg = <0x0144>;
 602                 ti,index-starts-at-one;
 603                 ti,invert-autoidle-bit;
 604         };
 605
 606         dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
 607                 #clock-cells = <0>;
 608                 compatible = "ti,divider-clock";
 609                 clocks = <&dpll_core_x2_ck>;
 610                 ti,max-div = <63>;
 611                 ti,autoidle-shift = <8>;
 612                 reg = <0x0154>;
 613                 ti,index-starts-at-one;
 614                 ti,invert-autoidle-bit;
 615         };
 616
 617         dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
 618                 #clock-cells = <0>;
 619                 compatible = "ti,divider-clock";
 620                 clocks = <&dpll_core_x2_ck>;
 621                 ti,max-div = <63>;
 622                 ti,autoidle-shift = <8>;
 623                 reg = <0x0158>;
 624                 ti,index-starts-at-one;
 625                 ti,invert-autoidle-bit;
 626         };
 627
 628         dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
 629                 #clock-cells = <0>;
 630                 compatible = "ti,divider-clock";
 631                 clocks = <&dpll_core_x2_ck>;
 632                 ti,max-div = <63>;
 633                 ti,autoidle-shift = <8>;
 634                 reg = <0x015c>;
 635                 ti,index-starts-at-one;
 636                 ti,invert-autoidle-bit;
 637         };
 638
 639         dpll_ddr_x2_ck: dpll_ddr_x2_ck {
 640                 #clock-cells = <0>;
 641                 compatible = "ti,omap4-dpll-x2-clock";
 642                 clocks = <&dpll_ddr_ck>;
 643         };
 644
 645         dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 {
 646                 #clock-cells = <0>;
 647                 compatible = "ti,divider-clock";
 648                 clocks = <&dpll_ddr_x2_ck>;
 649                 ti,max-div = <63>;
 650                 ti,autoidle-shift = <8>;
 651                 reg = <0x0228>;
 652                 ti,index-starts-at-one;
 653                 ti,invert-autoidle-bit;
 654         };
 655
 656         dpll_dsp_x2_ck: dpll_dsp_x2_ck {
 657                 #clock-cells = <0>;
 658                 compatible = "ti,omap4-dpll-x2-clock";
 659                 clocks = <&dpll_dsp_ck>;
 660         };
 661
 662         dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 {
 663                 #clock-cells = <0>;
 664                 compatible = "ti,divider-clock";
 665                 clocks = <&dpll_dsp_x2_ck>;
 666                 ti,max-div = <31>;
 667                 ti,autoidle-shift = <8>;
 668                 reg = <0x0248>;
 669                 ti,index-starts-at-one;
 670                 ti,invert-autoidle-bit;
 671                 assigned-clocks = <&dpll_dsp_m3x2_ck>;
 672                 assigned-clock-rates = <400000000>;
 673         };
 674
 675         dpll_gmac_x2_ck: dpll_gmac_x2_ck {
 676                 #clock-cells = <0>;
 677                 compatible = "ti,omap4-dpll-x2-clock";
 678                 clocks = <&dpll_gmac_ck>;
 679         };
 680
 681         dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 {
 682                 #clock-cells = <0>;
 683                 compatible = "ti,divider-clock";
 684                 clocks = <&dpll_gmac_x2_ck>;
 685                 ti,max-div = <63>;
 686                 ti,autoidle-shift = <8>;
 687                 reg = <0x02c0>;
 688                 ti,index-starts-at-one;
 689                 ti,invert-autoidle-bit;
 690         };
 691
 692         dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 {
 693                 #clock-cells = <0>;
 694                 compatible = "ti,divider-clock";
 695                 clocks = <&dpll_gmac_x2_ck>;
 696                 ti,max-div = <63>;
 697                 ti,autoidle-shift = <8>;
 698                 reg = <0x02c4>;
 699                 ti,index-starts-at-one;
 700                 ti,invert-autoidle-bit;
 701         };
 702
 703         dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 {
 704                 #clock-cells = <0>;
 705                 compatible = "ti,divider-clock";
 706                 clocks = <&dpll_gmac_x2_ck>;
 707                 ti,max-div = <63>;
 708                 ti,autoidle-shift = <8>;
 709                 reg = <0x02c8>;
 710                 ti,index-starts-at-one;
 711                 ti,invert-autoidle-bit;
 712         };
 713
 714         dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc {
 715                 #clock-cells = <0>;
 716                 compatible = "ti,divider-clock";
 717                 clocks = <&dpll_gmac_x2_ck>;
 718                 ti,max-div = <31>;
 719                 ti,autoidle-shift = <8>;
 720                 reg = <0x02bc>;
 721                 ti,index-starts-at-one;
 722                 ti,invert-autoidle-bit;
 723         };
 724
 725         gmii_m_clk_div: gmii_m_clk_div {
 726                 #clock-cells = <0>;
 727                 compatible = "fixed-factor-clock";
 728                 clocks = <&dpll_gmac_h11x2_ck>;
 729                 clock-mult = <1>;
 730                 clock-div = <2>;
 731         };
 732
 733         hdmi_clk2_div: hdmi_clk2_div {
 734                 #clock-cells = <0>;
 735                 compatible = "fixed-factor-clock";
 736                 clocks = <&hdmi_clkin_ck>;
 737                 clock-mult = <1>;
 738                 clock-div = <1>;
 739         };
 740
 741         hdmi_div_clk: hdmi_div_clk {
 742                 #clock-cells = <0>;
 743                 compatible = "fixed-factor-clock";
 744                 clocks = <&hdmi_clkin_ck>;
 745                 clock-mult = <1>;
 746                 clock-div = <1>;
 747         };
 748
 749         l3_iclk_div: l3_iclk_div@100 {
 750                 #clock-cells = <0>;
 751                 compatible = "ti,divider-clock";
 752                 ti,max-div = <2>;
 753                 ti,bit-shift = <4>;
 754                 reg = <0x0100>;
 755                 clocks = <&dpll_core_h12x2_ck>;
 756                 ti,index-power-of-two;
 757         };
 758
 759         l4_root_clk_div: l4_root_clk_div {
 760                 #clock-cells = <0>;
 761                 compatible = "fixed-factor-clock";
 762                 clocks = <&l3_iclk_div>;
 763                 clock-mult = <1>;
 764                 clock-div = <2>;
 765         };
 766
 767         video1_clk2_div: video1_clk2_div {
 768                 #clock-cells = <0>;
 769                 compatible = "fixed-factor-clock";
 770                 clocks = <&video1_clkin_ck>;
 771                 clock-mult = <1>;
 772                 clock-div = <1>;
 773         };
 774
 775         video1_div_clk: video1_div_clk {
 776                 #clock-cells = <0>;
 777                 compatible = "fixed-factor-clock";
 778                 clocks = <&video1_clkin_ck>;
 779                 clock-mult = <1>;
 780                 clock-div = <1>;
 781         };
 782
 783         video2_clk2_div: video2_clk2_div {
 784                 #clock-cells = <0>;
 785                 compatible = "fixed-factor-clock";
 786                 clocks = <&video2_clkin_ck>;
 787                 clock-mult = <1>;
 788                 clock-div = <1>;
 789         };
 790
 791         video2_div_clk: video2_div_clk {
 792                 #clock-cells = <0>;
 793                 compatible = "fixed-factor-clock";
 794                 clocks = <&video2_clkin_ck>;
 795                 clock-mult = <1>;
 796                 clock-div = <1>;
 797         };
 798
 799         dummy_ck: dummy_ck {
 800                 #clock-cells = <0>;
 801                 compatible = "fixed-clock";
 802                 clock-frequency = <0>;
 803         };
 804 };
 805 &prm_clocks {
 806         sys_clkin1: sys_clkin1@110 {
 807                 #clock-cells = <0>;
 808                 compatible = "ti,mux-clock";
 809                 clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
 810                 reg = <0x0110>;
 811                 ti,index-starts-at-one;
 812         };
 813
 814         abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 {
 815                 #clock-cells = <0>;
 816                 compatible = "ti,mux-clock";
 817                 clocks = <&sys_clkin1>, <&sys_clkin2>;
 818                 reg = <0x0118>;
 819         };
 820
 821         abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 {
 822                 #clock-cells = <0>;
 823                 compatible = "ti,mux-clock";
 824                 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
 825                 reg = <0x0114>;
 826         };
 827
 828         abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
 829                 #clock-cells = <0>;
 830                 compatible = "ti,mux-clock";
 831                 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
 832                 reg = <0x010c>;
 833         };
 834
 835         abe_24m_fclk: abe_24m_fclk@11c {
 836                 #clock-cells = <0>;
 837                 compatible = "ti,divider-clock";
 838                 clocks = <&dpll_abe_m2x2_ck>;
 839                 reg = <0x011c>;
 840                 ti,dividers = <8>, <16>;
 841         };
 842
 843         aess_fclk: aess_fclk@178 {
 844                 #clock-cells = <0>;
 845                 compatible = "ti,divider-clock";
 846                 clocks = <&abe_clk>;
 847                 reg = <0x0178>;
 848                 ti,max-div = <2>;
 849         };
 850
 851         abe_giclk_div: abe_giclk_div@174 {
 852                 #clock-cells = <0>;
 853                 compatible = "ti,divider-clock";
 854                 clocks = <&aess_fclk>;
 855                 reg = <0x0174>;
 856                 ti,max-div = <2>;
 857         };
 858
 859         abe_lp_clk_div: abe_lp_clk_div@1d8 {
 860                 #clock-cells = <0>;
 861                 compatible = "ti,divider-clock";
 862                 clocks = <&dpll_abe_m2x2_ck>;
 863                 reg = <0x01d8>;
 864                 ti,dividers = <16>, <32>;
 865         };
 866
 867         abe_sys_clk_div: abe_sys_clk_div@120 {
 868                 #clock-cells = <0>;
 869                 compatible = "ti,divider-clock";
 870                 clocks = <&sys_clkin1>;
 871                 reg = <0x0120>;
 872                 ti,max-div = <2>;
 873         };
 874
 875         adc_gfclk_mux: adc_gfclk_mux@1dc {
 876                 #clock-cells = <0>;
 877                 compatible = "ti,mux-clock";
 878                 clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
 879                 reg = <0x01dc>;
 880         };
 881
 882         sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 {
 883                 #clock-cells = <0>;
 884                 compatible = "ti,divider-clock";
 885                 clocks = <&sys_clkin1>;
 886                 ti,max-div = <64>;
 887                 reg = <0x01c8>;
 888                 ti,index-power-of-two;
 889         };
 890
 891         sys_clk2_dclk_div: sys_clk2_dclk_div@1cc {
 892                 #clock-cells = <0>;
 893                 compatible = "ti,divider-clock";
 894                 clocks = <&sys_clkin2>;
 895                 ti,max-div = <64>;
 896                 reg = <0x01cc>;
 897                 ti,index-power-of-two;
 898         };
 899
 900         per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc {
 901                 #clock-cells = <0>;
 902                 compatible = "ti,divider-clock";
 903                 clocks = <&dpll_abe_m2_ck>;
 904                 ti,max-div = <64>;
 905                 reg = <0x01bc>;
 906                 ti,index-power-of-two;
 907         };
 908
 909         dsp_gclk_div: dsp_gclk_div@18c {
 910                 #clock-cells = <0>;
 911                 compatible = "ti,divider-clock";
 912                 clocks = <&dpll_dsp_m2_ck>;
 913                 ti,max-div = <64>;
 914                 reg = <0x018c>;
 915                 ti,index-power-of-two;
 916         };
 917
 918         gpu_dclk: gpu_dclk@1a0 {
 919                 #clock-cells = <0>;
 920                 compatible = "ti,divider-clock";
 921                 clocks = <&dpll_gpu_m2_ck>;
 922                 ti,max-div = <64>;
 923                 reg = <0x01a0>;
 924                 ti,index-power-of-two;
 925         };
 926
 927         emif_phy_dclk_div: emif_phy_dclk_div@190 {
 928                 #clock-cells = <0>;
 929                 compatible = "ti,divider-clock";
 930                 clocks = <&dpll_ddr_m2_ck>;
 931                 ti,max-div = <64>;
 932                 reg = <0x0190>;
 933                 ti,index-power-of-two;
 934         };
 935
 936         gmac_250m_dclk_div: gmac_250m_dclk_div@19c {
 937                 #clock-cells = <0>;
 938                 compatible = "ti,divider-clock";
 939                 clocks = <&dpll_gmac_m2_ck>;
 940                 ti,max-div = <64>;
 941                 reg = <0x019c>;
 942                 ti,index-power-of-two;
 943         };
 944
 945         gmac_main_clk: gmac_main_clk {
 946                 #clock-cells = <0>;
 947                 compatible = "fixed-factor-clock";
 948                 clocks = <&gmac_250m_dclk_div>;
 949                 clock-mult = <1>;
 950                 clock-div = <2>;
 951         };
 952
 953         l3init_480m_dclk_div: l3init_480m_dclk_div@1ac {
 954                 #clock-cells = <0>;
 955                 compatible = "ti,divider-clock";
 956                 clocks = <&dpll_usb_m2_ck>;
 957                 ti,max-div = <64>;
 958                 reg = <0x01ac>;
 959                 ti,index-power-of-two;
 960         };
 961
 962         usb_otg_dclk_div: usb_otg_dclk_div@184 {
 963                 #clock-cells = <0>;
 964                 compatible = "ti,divider-clock";
 965                 clocks = <&usb_otg_clkin_ck>;
 966                 ti,max-div = <64>;
 967                 reg = <0x0184>;
 968                 ti,index-power-of-two;
 969         };
 970
 971         sata_dclk_div: sata_dclk_div@1c0 {
 972                 #clock-cells = <0>;
 973                 compatible = "ti,divider-clock";
 974                 clocks = <&sys_clkin1>;
 975                 ti,max-div = <64>;
 976                 reg = <0x01c0>;
 977                 ti,index-power-of-two;
 978         };
 979
 980         pcie2_dclk_div: pcie2_dclk_div@1b8 {
 981                 #clock-cells = <0>;
 982                 compatible = "ti,divider-clock";
 983                 clocks = <&dpll_pcie_ref_m2_ck>;
 984                 ti,max-div = <64>;
 985                 reg = <0x01b8>;
 986                 ti,index-power-of-two;
 987         };
 988
 989         pcie_dclk_div: pcie_dclk_div@1b4 {
 990                 #clock-cells = <0>;
 991                 compatible = "ti,divider-clock";
 992                 clocks = <&apll_pcie_m2_ck>;
 993                 ti,max-div = <64>;
 994                 reg = <0x01b4>;
 995                 ti,index-power-of-two;
 996         };
 997
 998         emu_dclk_div: emu_dclk_div@194 {
 999                 #clock-cells = <0>;
1000                 compatible = "ti,divider-clock";
1001                 clocks = <&sys_clkin1>;
1002                 ti,max-div = <64>;
1003                 reg = <0x0194>;
1004                 ti,index-power-of-two;
1005         };
1006
1007         secure_32k_dclk_div: secure_32k_dclk_div@1c4 {
1008                 #clock-cells = <0>;
1009                 compatible = "ti,divider-clock";
1010                 clocks = <&secure_32k_clk_src_ck>;
1011                 ti,max-div = <64>;
1012                 reg = <0x01c4>;
1013                 ti,index-power-of-two;
1014         };
1015
1016         clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 {
1017                 #clock-cells = <0>;
1018                 compatible = "ti,mux-clock";
1019                 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1020                 reg = <0x0158>;
1021         };
1022
1023         clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c {
1024                 #clock-cells = <0>;
1025                 compatible = "ti,mux-clock";
1026                 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1027                 reg = <0x015c>;
1028         };
1029
1030         clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 {
1031                 #clock-cells = <0>;
1032                 compatible = "ti,mux-clock";
1033                 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1034                 reg = <0x0160>;
1035         };
1036
1037         custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
1038                 #clock-cells = <0>;
1039                 compatible = "fixed-factor-clock";
1040                 clocks = <&sys_clkin1>;
1041                 clock-mult = <1>;
1042                 clock-div = <2>;
1043         };
1044
1045         eve_clk: eve_clk@180 {
1046                 #clock-cells = <0>;
1047                 compatible = "ti,mux-clock";
1048                 clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
1049                 reg = <0x0180>;
1050         };
1051
1052         hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 {
1053                 #clock-cells = <0>;
1054                 compatible = "ti,mux-clock";
1055                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1056                 reg = <0x0164>;
1057         };
1058
1059         mlb_clk: mlb_clk@134 {
1060                 #clock-cells = <0>;
1061                 compatible = "ti,divider-clock";
1062                 clocks = <&mlb_clkin_ck>;
1063                 ti,max-div = <64>;
1064                 reg = <0x0134>;
1065                 ti,index-power-of-two;
1066         };
1067
1068         mlbp_clk: mlbp_clk@130 {
1069                 #clock-cells = <0>;
1070                 compatible = "ti,divider-clock";
1071                 clocks = <&mlbp_clkin_ck>;
1072                 ti,max-div = <64>;
1073                 reg = <0x0130>;
1074                 ti,index-power-of-two;
1075         };
1076
1077         per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 {
1078                 #clock-cells = <0>;
1079                 compatible = "ti,divider-clock";
1080                 clocks = <&dpll_abe_m2_ck>;
1081                 ti,max-div = <64>;
1082                 reg = <0x0138>;
1083                 ti,index-power-of-two;
1084         };
1085
1086         timer_sys_clk_div: timer_sys_clk_div@144 {
1087                 #clock-cells = <0>;
1088                 compatible = "ti,divider-clock";
1089                 clocks = <&sys_clkin1>;
1090                 reg = <0x0144>;
1091                 ti,max-div = <2>;
1092         };
1093
1094         video1_dpll_clk_mux: video1_dpll_clk_mux@168 {
1095                 #clock-cells = <0>;
1096                 compatible = "ti,mux-clock";
1097                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1098                 reg = <0x0168>;
1099         };
1100
1101         video2_dpll_clk_mux: video2_dpll_clk_mux@16c {
1102                 #clock-cells = <0>;
1103                 compatible = "ti,mux-clock";
1104                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1105                 reg = <0x016c>;
1106         };
1107
1108         wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
1109                 #clock-cells = <0>;
1110                 compatible = "ti,mux-clock";
1111                 clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
1112                 reg = <0x0108>;
1113         };
1114 };
1115
1116 &cm_core_clocks {
1117         dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {
1118                 #clock-cells = <0>;
1119                 compatible = "ti,omap4-dpll-clock";
1120                 clocks = <&sys_clkin1>, <&sys_clkin1>;
1121                 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
1122         };
1123
1124         dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 {
1125                 #clock-cells = <0>;
1126                 compatible = "ti,divider-clock";
1127                 clocks = <&dpll_pcie_ref_ck>;
1128                 ti,max-div = <31>;
1129                 ti,autoidle-shift = <8>;
1130                 reg = <0x0210>;
1131                 ti,index-starts-at-one;
1132                 ti,invert-autoidle-bit;
1133         };
1134
1135         apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
1136                 compatible = "ti,mux-clock";
1137                 clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
1138                 #clock-cells = <0>;
1139                 reg = <0x021c 0x4>;
1140                 ti,bit-shift = <7>;
1141         };
1142
1143         apll_pcie_ck: apll_pcie_ck@21c {
1144                 #clock-cells = <0>;
1145                 compatible = "ti,dra7-apll-clock";
1146                 clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
1147                 reg = <0x021c>, <0x0220>;
1148         };
1149
1150         optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
1151                 compatible = "ti,divider-clock";
1152                 clocks = <&apll_pcie_ck>;
1153                 #clock-cells = <0>;
1154                 reg = <0x021c>;
1155                 ti,dividers = <2>, <1>;
1156                 ti,bit-shift = <8>;
1157                 ti,max-div = <2>;
1158         };
1159
1160         apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
1161                 #clock-cells = <0>;
1162                 compatible = "fixed-factor-clock";
1163                 clocks = <&apll_pcie_ck>;
1164                 clock-mult = <1>;
1165                 clock-div = <1>;
1166         };
1167
1168         apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
1169                 #clock-cells = <0>;
1170                 compatible = "fixed-factor-clock";
1171                 clocks = <&apll_pcie_ck>;
1172                 clock-mult = <1>;
1173                 clock-div = <1>;
1174         };
1175
1176         apll_pcie_m2_ck: apll_pcie_m2_ck {
1177                 #clock-cells = <0>;
1178                 compatible = "fixed-factor-clock";
1179                 clocks = <&apll_pcie_ck>;
1180                 clock-mult = <1>;
1181                 clock-div = <1>;
1182         };
1183
1184         dpll_per_byp_mux: dpll_per_byp_mux@14c {
1185                 #clock-cells = <0>;
1186                 compatible = "ti,mux-clock";
1187                 clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
1188                 ti,bit-shift = <23>;
1189                 reg = <0x014c>;
1190         };
1191
1192         dpll_per_ck: dpll_per_ck@140 {
1193                 #clock-cells = <0>;
1194                 compatible = "ti,omap4-dpll-clock";
1195                 clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
1196                 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
1197         };
1198
1199         dpll_per_m2_ck: dpll_per_m2_ck@150 {
1200                 #clock-cells = <0>;
1201                 compatible = "ti,divider-clock";
1202                 clocks = <&dpll_per_ck>;
1203                 ti,max-div = <31>;
1204                 ti,autoidle-shift = <8>;
1205                 reg = <0x0150>;
1206                 ti,index-starts-at-one;
1207                 ti,invert-autoidle-bit;
1208         };
1209
1210         func_96m_aon_dclk_div: func_96m_aon_dclk_div {
1211                 #clock-cells = <0>;
1212                 compatible = "fixed-factor-clock";
1213                 clocks = <&dpll_per_m2_ck>;
1214                 clock-mult = <1>;
1215                 clock-div = <1>;
1216         };
1217
1218         dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
1219                 #clock-cells = <0>;
1220                 compatible = "ti,mux-clock";
1221                 clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
1222                 ti,bit-shift = <23>;
1223                 reg = <0x018c>;
1224         };
1225
1226         dpll_usb_ck: dpll_usb_ck@180 {
1227                 #clock-cells = <0>;
1228                 compatible = "ti,omap4-dpll-j-type-clock";
1229                 clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
1230                 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
1231         };
1232
1233         dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
1234                 #clock-cells = <0>;
1235                 compatible = "ti,divider-clock";
1236                 clocks = <&dpll_usb_ck>;
1237                 ti,max-div = <127>;
1238                 ti,autoidle-shift = <8>;
1239                 reg = <0x0190>;
1240                 ti,index-starts-at-one;
1241                 ti,invert-autoidle-bit;
1242         };
1243
1244         dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 {
1245                 #clock-cells = <0>;
1246                 compatible = "ti,divider-clock";
1247                 clocks = <&dpll_pcie_ref_ck>;
1248                 ti,max-div = <127>;
1249                 ti,autoidle-shift = <8>;
1250                 reg = <0x0210>;
1251                 ti,index-starts-at-one;
1252                 ti,invert-autoidle-bit;
1253         };
1254
1255         dpll_per_x2_ck: dpll_per_x2_ck {
1256                 #clock-cells = <0>;
1257                 compatible = "ti,omap4-dpll-x2-clock";
1258                 clocks = <&dpll_per_ck>;
1259         };
1260
1261         dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
1262                 #clock-cells = <0>;
1263                 compatible = "ti,divider-clock";
1264                 clocks = <&dpll_per_x2_ck>;
1265                 ti,max-div = <63>;
1266                 ti,autoidle-shift = <8>;
1267                 reg = <0x0158>;
1268                 ti,index-starts-at-one;
1269                 ti,invert-autoidle-bit;
1270         };
1271
1272         dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
1273                 #clock-cells = <0>;
1274                 compatible = "ti,divider-clock";
1275                 clocks = <&dpll_per_x2_ck>;
1276                 ti,max-div = <63>;
1277                 ti,autoidle-shift = <8>;
1278                 reg = <0x015c>;
1279                 ti,index-starts-at-one;
1280                 ti,invert-autoidle-bit;
1281         };
1282
1283         dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 {
1284                 #clock-cells = <0>;
1285                 compatible = "ti,divider-clock";
1286                 clocks = <&dpll_per_x2_ck>;
1287                 ti,max-div = <63>;
1288                 ti,autoidle-shift = <8>;
1289                 reg = <0x0160>;
1290                 ti,index-starts-at-one;
1291                 ti,invert-autoidle-bit;
1292         };
1293
1294         dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
1295                 #clock-cells = <0>;
1296                 compatible = "ti,divider-clock";
1297                 clocks = <&dpll_per_x2_ck>;
1298                 ti,max-div = <63>;
1299                 ti,autoidle-shift = <8>;
1300                 reg = <0x0164>;
1301                 ti,index-starts-at-one;
1302                 ti,invert-autoidle-bit;
1303         };
1304
1305         dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
1306                 #clock-cells = <0>;
1307                 compatible = "ti,divider-clock";
1308                 clocks = <&dpll_per_x2_ck>;
1309                 ti,max-div = <31>;
1310                 ti,autoidle-shift = <8>;
1311                 reg = <0x0150>;
1312                 ti,index-starts-at-one;
1313                 ti,invert-autoidle-bit;
1314         };
1315
1316         dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
1317                 #clock-cells = <0>;
1318                 compatible = "fixed-factor-clock";
1319                 clocks = <&dpll_usb_ck>;
1320                 clock-mult = <1>;
1321                 clock-div = <1>;
1322         };
1323
1324         func_128m_clk: func_128m_clk {
1325                 #clock-cells = <0>;
1326                 compatible = "fixed-factor-clock";
1327                 clocks = <&dpll_per_h11x2_ck>;
1328                 clock-mult = <1>;
1329                 clock-div = <2>;
1330         };
1331
1332         func_12m_fclk: func_12m_fclk {
1333                 #clock-cells = <0>;
1334                 compatible = "fixed-factor-clock";
1335                 clocks = <&dpll_per_m2x2_ck>;
1336                 clock-mult = <1>;
1337                 clock-div = <16>;
1338         };
1339
1340         func_24m_clk: func_24m_clk {
1341                 #clock-cells = <0>;
1342                 compatible = "fixed-factor-clock";
1343                 clocks = <&dpll_per_m2_ck>;
1344                 clock-mult = <1>;
1345                 clock-div = <4>;
1346         };
1347
1348         func_48m_fclk: func_48m_fclk {
1349                 #clock-cells = <0>;
1350                 compatible = "fixed-factor-clock";
1351                 clocks = <&dpll_per_m2x2_ck>;
1352                 clock-mult = <1>;
1353                 clock-div = <4>;
1354         };
1355
1356         func_96m_fclk: func_96m_fclk {
1357                 #clock-cells = <0>;
1358                 compatible = "fixed-factor-clock";
1359                 clocks = <&dpll_per_m2x2_ck>;
1360                 clock-mult = <1>;
1361                 clock-div = <2>;
1362         };
1363
1364         l3init_60m_fclk: l3init_60m_fclk@104 {
1365                 #clock-cells = <0>;
1366                 compatible = "ti,divider-clock";
1367                 clocks = <&dpll_usb_m2_ck>;
1368                 reg = <0x0104>;
1369                 ti,dividers = <1>, <8>;
1370         };
1371
1372         clkout2_clk: clkout2_clk@6b0 {
1373                 #clock-cells = <0>;
1374                 compatible = "ti,gate-clock";
1375                 clocks = <&clkoutmux2_clk_mux>;
1376                 ti,bit-shift = <8>;
1377                 reg = <0x06b0>;
1378         };
1379
1380         l3init_960m_gfclk: l3init_960m_gfclk@6c0 {
1381                 #clock-cells = <0>;
1382                 compatible = "ti,gate-clock";
1383                 clocks = <&dpll_usb_clkdcoldo>;
1384                 ti,bit-shift = <8>;
1385                 reg = <0x06c0>;
1386         };
1387
1388         usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {
1389                 #clock-cells = <0>;
1390                 compatible = "ti,gate-clock";
1391                 clocks = <&sys_32k_ck>;
1392                 ti,bit-shift = <8>;
1393                 reg = <0x0640>;
1394         };
1395
1396         usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 {
1397                 #clock-cells = <0>;
1398                 compatible = "ti,gate-clock";
1399                 clocks = <&sys_32k_ck>;
1400                 ti,bit-shift = <8>;
1401                 reg = <0x0688>;
1402         };
1403
1404         usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 {
1405                 #clock-cells = <0>;
1406                 compatible = "ti,gate-clock";
1407                 clocks = <&sys_32k_ck>;
1408                 ti,bit-shift = <8>;
1409                 reg = <0x0698>;
1410         };
1411
1412         gpu_core_gclk_mux: gpu_core_gclk_mux@1220 {
1413                 #clock-cells = <0>;
1414                 compatible = "ti,mux-clock";
1415                 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1416                 ti,bit-shift = <24>;
1417                 reg = <0x1220>;
1418                 assigned-clocks = <&gpu_core_gclk_mux>;
1419                 assigned-clock-parents = <&dpll_gpu_m2_ck>;
1420         };
1421
1422         gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
1423                 #clock-cells = <0>;
1424                 compatible = "ti,mux-clock";
1425                 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1426                 ti,bit-shift = <26>;
1427                 reg = <0x1220>;
1428                 assigned-clocks = <&gpu_hyd_gclk_mux>;
1429                 assigned-clock-parents = <&dpll_gpu_m2_ck>;
1430         };
1431
1432         l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
1433                 #clock-cells = <0>;
1434                 compatible = "ti,divider-clock";
1435                 clocks = <&wkupaon_iclk_mux>;
1436                 ti,bit-shift = <24>;
1437                 reg = <0x0e50>;
1438                 ti,dividers = <8>, <16>, <32>;
1439         };
1440
1441         vip1_gclk_mux: vip1_gclk_mux@1020 {
1442                 #clock-cells = <0>;
1443                 compatible = "ti,mux-clock";
1444                 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
1445                 ti,bit-shift = <24>;
1446                 reg = <0x1020>;
1447         };
1448
1449         vip2_gclk_mux: vip2_gclk_mux@1028 {
1450                 #clock-cells = <0>;
1451                 compatible = "ti,mux-clock";
1452                 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
1453                 ti,bit-shift = <24>;
1454                 reg = <0x1028>;
1455         };
1456
1457         vip3_gclk_mux: vip3_gclk_mux@1030 {
1458                 #clock-cells = <0>;
1459                 compatible = "ti,mux-clock";
1460                 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
1461                 ti,bit-shift = <24>;
1462                 reg = <0x1030>;
1463         };
1464 };
1465
1466 &cm_core_clockdomains {
1467         coreaon_clkdm: coreaon_clkdm {
1468                 compatible = "ti,clockdomain";
1469                 clocks = <&dpll_usb_ck>;
1470         };
1471 };
1472
1473 &scm_conf_clocks {
1474         dss_deshdcp_clk: dss_deshdcp_clk@558 {
1475                 #clock-cells = <0>;
1476                 compatible = "ti,gate-clock";
1477                 clocks = <&l3_iclk_div>;
1478                 ti,bit-shift = <0>;
1479                 reg = <0x558>;
1480         };
1481
1482        ehrpwm0_tbclk: ehrpwm0_tbclk@558 {
1483                 #clock-cells = <0>;
1484                 compatible = "ti,gate-clock";
1485                 clocks = <&l4_root_clk_div>;
1486                 ti,bit-shift = <20>;
1487                 reg = <0x0558>;
1488         };
1489
1490         ehrpwm1_tbclk: ehrpwm1_tbclk@558 {
1491                 #clock-cells = <0>;
1492                 compatible = "ti,gate-clock";
1493                 clocks = <&l4_root_clk_div>;
1494                 ti,bit-shift = <21>;
1495                 reg = <0x0558>;
1496         };
1497
1498         ehrpwm2_tbclk: ehrpwm2_tbclk@558 {
1499                 #clock-cells = <0>;
1500                 compatible = "ti,gate-clock";
1501                 clocks = <&l4_root_clk_div>;
1502                 ti,bit-shift = <22>;
1503                 reg = <0x0558>;
1504         };
1505
1506         sys_32k_ck: sys_32k_ck {
1507                 #clock-cells = <0>;
1508                 compatible = "ti,mux-clock";
1509                 clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
1510                 ti,bit-shift = <8>;
1511                 reg = <0x6c4>;
1512         };
1513 };
1514
1515 &cm_core_aon {
1516         mpu_cm: mpu-cm@300 {
1517                 compatible = "ti,omap4-cm";
1518                 reg = <0x300 0x100>;
1519                 #address-cells = <1>;
1520                 #size-cells = <1>;
1521                 ranges = <0 0x300 0x100>;
1522
1523                 mpu_clkctrl: mpu-clkctrl@20 {
1524                         compatible = "ti,clkctrl";
1525                         reg = <0x20 0x4>;
1526                         #clock-cells = <2>;
1527                 };
1528
1529         };
1530
1531         dsp1_cm: dsp1-cm@400 {
1532                 compatible = "ti,omap4-cm";
1533                 reg = <0x400 0x100>;
1534                 #address-cells = <1>;
1535                 #size-cells = <1>;
1536                 ranges = <0 0x400 0x100>;
1537
1538                 dsp1_clkctrl: dsp1-clkctrl@20 {
1539                         compatible = "ti,clkctrl";
1540                         reg = <0x20 0x4>;
1541                         #clock-cells = <2>;
1542                 };
1543
1544         };
1545
1546         ipu_cm: ipu-cm@500 {
1547                 compatible = "ti,omap4-cm";
1548                 reg = <0x500 0x100>;
1549                 #address-cells = <1>;
1550                 #size-cells = <1>;
1551                 ranges = <0 0x500 0x100>;
1552
1553                 ipu1_clkctrl: ipu1-clkctrl@20 {
1554                         compatible = "ti,clkctrl";
1555                         reg = <0x20 0x4>;
1556                         #clock-cells = <2>;
1557                         assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>;
1558                         assigned-clock-parents = <&dpll_core_h22x2_ck>;
1559                 };
1560
1561                 ipu_clkctrl: ipu-clkctrl@50 {
1562                         compatible = "ti,clkctrl";
1563                         reg = <0x50 0x34>;
1564                         #clock-cells = <2>;
1565                 };
1566
1567         };
1568
1569         dsp2_cm: dsp2-cm@600 {
1570                 compatible = "ti,omap4-cm";
1571                 reg = <0x600 0x100>;
1572                 #address-cells = <1>;
1573                 #size-cells = <1>;
1574                 ranges = <0 0x600 0x100>;
1575
1576                 dsp2_clkctrl: dsp2-clkctrl@20 {
1577                         compatible = "ti,clkctrl";
1578                         reg = <0x20 0x4>;
1579                         #clock-cells = <2>;
1580                 };
1581
1582         };
1583
1584         rtc_cm: rtc-cm@700 {
1585                 compatible = "ti,omap4-cm";
1586                 reg = <0x700 0x60>;
1587                 #address-cells = <1>;
1588                 #size-cells = <1>;
1589                 ranges = <0 0x700 0x60>;
1590
1591                 rtc_clkctrl: rtc-clkctrl@20 {
1592                         compatible = "ti,clkctrl";
1593                         reg = <0x20 0x28>;
1594                         #clock-cells = <2>;
1595                 };
1596         };
1597
1598         vpe_cm: vpe-cm@760 {
1599                 compatible = "ti,omap4-cm";
1600                 reg = <0x760 0xc>;
1601                 #address-cells = <1>;
1602                 #size-cells = <1>;
1603                 ranges = <0 0x760 0xc>;
1604
1605                 vpe_clkctrl: vpe-clkctrl@0 {
1606                         compatible = "ti,clkctrl";
1607                         reg = <0x0 0xc>;
1608                         #clock-cells = <2>;
1609                 };
1610         };
1611
1612 };
1613
1614 &cm_core {
1615         coreaon_cm: coreaon-cm@600 {
1616                 compatible = "ti,omap4-cm";
1617                 reg = <0x600 0x100>;
1618                 #address-cells = <1>;
1619                 #size-cells = <1>;
1620                 ranges = <0 0x600 0x100>;
1621
1622                 coreaon_clkctrl: coreaon-clkctrl@20 {
1623                         compatible = "ti,clkctrl";
1624                         reg = <0x20 0x1c>;
1625                         #clock-cells = <2>;
1626                 };
1627         };
1628
1629         l3main1_cm: l3main1-cm@700 {
1630                 compatible = "ti,omap4-cm";
1631                 reg = <0x700 0x100>;
1632                 #address-cells = <1>;
1633                 #size-cells = <1>;
1634                 ranges = <0 0x700 0x100>;
1635
1636                 l3main1_clkctrl: l3main1-clkctrl@20 {
1637                         compatible = "ti,clkctrl";
1638                         reg = <0x20 0x74>;
1639                         #clock-cells = <2>;
1640                 };
1641
1642         };
1643
1644         ipu2_cm: ipu2-cm@900 {
1645                 compatible = "ti,omap4-cm";
1646                 reg = <0x900 0x100>;
1647                 #address-cells = <1>;
1648                 #size-cells = <1>;
1649                 ranges = <0 0x900 0x100>;
1650
1651                 ipu2_clkctrl: ipu2-clkctrl@20 {
1652                         compatible = "ti,clkctrl";
1653                         reg = <0x20 0x4>;
1654                         #clock-cells = <2>;
1655                 };
1656
1657         };
1658
1659         dma_cm: dma-cm@a00 {
1660                 compatible = "ti,omap4-cm";
1661                 reg = <0xa00 0x100>;
1662                 #address-cells = <1>;
1663                 #size-cells = <1>;
1664                 ranges = <0 0xa00 0x100>;
1665
1666                 dma_clkctrl: dma-clkctrl@20 {
1667                         compatible = "ti,clkctrl";
1668                         reg = <0x20 0x4>;
1669                         #clock-cells = <2>;
1670                 };
1671         };
1672
1673         emif_cm: emif-cm@b00 {
1674                 compatible = "ti,omap4-cm";
1675                 reg = <0xb00 0x100>;
1676                 #address-cells = <1>;
1677                 #size-cells = <1>;
1678                 ranges = <0 0xb00 0x100>;
1679
1680                 emif_clkctrl: emif-clkctrl@20 {
1681                         compatible = "ti,clkctrl";
1682                         reg = <0x20 0x4>;
1683                         #clock-cells = <2>;
1684                 };
1685         };
1686
1687         atl_cm: atl-cm@c00 {
1688                 compatible = "ti,omap4-cm";
1689                 reg = <0xc00 0x100>;
1690                 #address-cells = <1>;
1691                 #size-cells = <1>;
1692                 ranges = <0 0xc00 0x100>;
1693
1694                 atl_clkctrl: atl-clkctrl@0 {
1695                         compatible = "ti,clkctrl";
1696                         reg = <0x0 0x4>;
1697                         #clock-cells = <2>;
1698                 };
1699         };
1700
1701         l4cfg_cm: l4cfg-cm@d00 {
1702                 compatible = "ti,omap4-cm";
1703                 reg = <0xd00 0x100>;
1704                 #address-cells = <1>;
1705                 #size-cells = <1>;
1706                 ranges = <0 0xd00 0x100>;
1707
1708                 l4cfg_clkctrl: l4cfg-clkctrl@20 {
1709                         compatible = "ti,clkctrl";
1710                         reg = <0x20 0x84>;
1711                         #clock-cells = <2>;
1712                 };
1713         };
1714
1715         l3instr_cm: l3instr-cm@e00 {
1716                 compatible = "ti,omap4-cm";
1717                 reg = <0xe00 0x100>;
1718                 #address-cells = <1>;
1719                 #size-cells = <1>;
1720                 ranges = <0 0xe00 0x100>;
1721
1722                 l3instr_clkctrl: l3instr-clkctrl@20 {
1723                         compatible = "ti,clkctrl";
1724                         reg = <0x20 0xc>;
1725                         #clock-cells = <2>;
1726                 };
1727         };
1728
1729         iva_cm: iva-cm@f00 {
1730                 compatible = "ti,omap4-cm";
1731                 reg = <0xf00 0x100>;
1732                 #address-cells = <1>;
1733                 #size-cells = <1>;
1734                 ranges = <0 0xf00 0x100>;
1735
1736                 iva_clkctrl: iva-clkctrl@20 {
1737                         compatible = "ti,clkctrl";
1738                         reg = <0x20 0xc>;
1739                         #clock-cells = <2>;
1740                 };
1741         };
1742
1743         cam_cm: cam-cm@1000 {
1744                 compatible = "ti,omap4-cm";
1745                 reg = <0x1000 0x100>;
1746                 #address-cells = <1>;
1747                 #size-cells = <1>;
1748                 ranges = <0 0x1000 0x100>;
1749
1750                 cam_clkctrl: cam-clkctrl@20 {
1751                         compatible = "ti,clkctrl";
1752                         reg = <0x20 0x2c>;
1753                         #clock-cells = <2>;
1754                 };
1755         };
1756
1757         dss_cm: dss-cm@1100 {
1758                 compatible = "ti,omap4-cm";
1759                 reg = <0x1100 0x100>;
1760                 #address-cells = <1>;
1761                 #size-cells = <1>;
1762                 ranges = <0 0x1100 0x100>;
1763
1764                 dss_clkctrl: dss-clkctrl@20 {
1765                         compatible = "ti,clkctrl";
1766                         reg = <0x20 0x14>;
1767                         #clock-cells = <2>;
1768                 };
1769         };
1770
1771         gpu_cm: gpu-cm@1200 {
1772                 compatible = "ti,omap4-cm";
1773                 reg = <0x1200 0x100>;
1774                 #address-cells = <1>;
1775                 #size-cells = <1>;
1776                 ranges = <0 0x1200 0x100>;
1777
1778                 gpu_clkctrl: gpu-clkctrl@20 {
1779                         compatible = "ti,clkctrl";
1780                         reg = <0x20 0x4>;
1781                         #clock-cells = <2>;
1782                 };
1783         };
1784
1785         l3init_cm: l3init-cm@1300 {
1786                 compatible = "ti,omap4-cm";
1787                 reg = <0x1300 0x100>;
1788                 #address-cells = <1>;
1789                 #size-cells = <1>;
1790                 ranges = <0 0x1300 0x100>;
1791
1792                 l3init_clkctrl: l3init-clkctrl@20 {
1793                         compatible = "ti,clkctrl";
1794                         reg = <0x20 0x6c>, <0xe0 0x14>;
1795                         #clock-cells = <2>;
1796                 };
1797
1798                 pcie_clkctrl: pcie-clkctrl@b0 {
1799                         compatible = "ti,clkctrl";
1800                         reg = <0xb0 0xc>;
1801                         #clock-cells = <2>;
1802                 };
1803
1804                 gmac_clkctrl: gmac-clkctrl@d0 {
1805                         compatible = "ti,clkctrl";
1806                         reg = <0xd0 0x4>;
1807                         #clock-cells = <2>;
1808                 };
1809
1810         };
1811
1812         l4per_cm: l4per-cm@1700 {
1813                 compatible = "ti,omap4-cm";
1814                 reg = <0x1700 0x300>;
1815                 #address-cells = <1>;
1816                 #size-cells = <1>;
1817                 ranges = <0 0x1700 0x300>;
1818
1819                 l4per_clkctrl: l4per-clkctrl@28 {
1820                         compatible = "ti,clkctrl";
1821                         reg = <0x28 0x64>, <0xa0 0x24>, <0xf0 0x3c>, <0x140 0x1c>, <0x170 0x4>;
1822                         #clock-cells = <2>;
1823
1824                         assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
1825                         assigned-clock-parents = <&abe_24m_fclk>;
1826                 };
1827
1828                 l4sec_clkctrl: l4sec-clkctrl@1a0 {
1829                         compatible = "ti,clkctrl";
1830                         reg = <0x1a0 0x2c>;
1831                         #clock-cells = <2>;
1832                 };
1833
1834                 l4per2_clkctrl: l4per2-clkctrl@c {
1835                         compatible = "ti,clkctrl";
1836                         reg = <0xc 0x4>, <0x18 0xc>, <0x90 0xc>, <0xc4 0x4>, <0x138 0x4>, <0x160 0xc>, <0x178 0x24>, <0x1d0 0x3c>;
1837                         #clock-cells = <2>;
1838                 };
1839
1840                 l4per3_clkctrl: l4per3-clkctrl@14 {
1841                         compatible = "ti,clkctrl";
1842                         reg = <0x14 0x4>, <0xc8 0x14>, <0x130 0x4>;
1843                         #clock-cells = <2>;
1844                 };
1845         };
1846
1847 };
1848
1849 &prm {
1850         wkupaon_cm: wkupaon-cm@1800 {
1851                 compatible = "ti,omap4-cm";
1852                 reg = <0x1800 0x100>;
1853                 #address-cells = <1>;
1854                 #size-cells = <1>;
1855                 ranges = <0 0x1800 0x100>;
1856
1857                 wkupaon_clkctrl: wkupaon-clkctrl@20 {
1858                         compatible = "ti,clkctrl";
1859                         reg = <0x20 0x6c>;
1860                         #clock-cells = <2>;
1861                 };
1862         };
1863 };