1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos3250 based ARTIK5 evaluation board device tree source
5 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
8 * Device tree source file for Samsung's ARTIK5 evaluation board
9 * which is based on Samsung Exynos3250 SoC.
13 #include "exynos3250-artik5.dtsi"
16 model = "Samsung ARTIK5 evaluation board";
17 compatible = "samsung,artik5-eval", "samsung,artik5",
18 "samsung,exynos3250", "samsung,exynos3";
24 vqmmc-supply = <&ldo3_reg>;
25 card-detect-delay = <200>;
26 clock-frequency = <100000000>;
27 max-frequency = <100000000>;
28 samsung,dw-mshc-ciu-div = <1>;
29 samsung,dw-mshc-sdr-timing = <0 1>;
30 samsung,dw-mshc-ddr-timing = <1 2>;
31 pinctrl-names = "default";
32 pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>;
43 cs-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>, <0>;
45 assigned-clocks = <&cmu CLK_MOUT_SPI0>, <&cmu CLK_DIV_SPI0>,
46 <&cmu CLK_DIV_SPI0_PRE>, <&cmu CLK_SCLK_SPI0>;
47 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>, /* for: CLK_MOUT_SPI0 */
48 <&cmu CLK_MOUT_SPI0>, /* for: CLK_DIV_SPI0 */
49 <&cmu CLK_DIV_SPI0>, /* for: CLK_DIV_SPI0_PRE */
50 <&cmu CLK_DIV_SPI0_PRE>; /* for: CLK_SCLK_SPI0 */
53 compatible = "asix,ax88796c";
55 local-mac-address = [00 00 00 00 00 00]; /* Filled in by a boot-loader */
56 interrupt-parent = <&gpx2>;
57 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
58 spi-max-frequency = <40000000>;
59 reset-gpios = <&gpe0 2 GPIO_ACTIVE_LOW>;
62 samsung,spi-feedback-delay = <2>;