arch/arm/boot/dts/exynos5410.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Samsung Exynos5410 SoC device tree source
   4  *
   5  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  *
   8  * Samsung Exynos5410 SoC device nodes are listed in this file.
   9  * Exynos5410 based board files can include this file and provide
  10  * values for board specfic bindings.
  11  */
  12
  13 #include "exynos54xx.dtsi"
  14 #include <dt-bindings/clock/exynos5410.h>
  15 #include <dt-bindings/clock/exynos-audss-clk.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17
  18 / {
  19         compatible = "samsung,exynos5410", "samsung,exynos5";
  20         interrupt-parent = <&gic>;
  21
  22         aliases {
  23                 pinctrl0 = &pinctrl_0;
  24                 pinctrl1 = &pinctrl_1;
  25                 pinctrl2 = &pinctrl_2;
  26                 pinctrl3 = &pinctrl_3;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 cpu0: cpu@0 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a15";
  36                         reg = <0x0>;
  37                         clock-frequency = <1600000000>;
  38                 };
  39
  40                 cpu1: cpu@1 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a15";
  43                         reg = <0x1>;
  44                         clock-frequency = <1600000000>;
  45                 };
  46
  47                 cpu2: cpu@2 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a15";
  50                         reg = <0x2>;
  51                         clock-frequency = <1600000000>;
  52                 };
  53
  54                 cpu3: cpu@3 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a15";
  57                         reg = <0x3>;
  58                         clock-frequency = <1600000000>;
  59                 };
  60         };
  61
  62         soc: soc {
  63                 compatible = "simple-bus";
  64                 #address-cells = <1>;
  65                 #size-cells = <1>;
  66                 ranges;
  67
  68                 pmu_system_controller: system-controller@10040000 {
  69                         compatible = "samsung,exynos5410-pmu", "syscon";
  70                         reg = <0x10040000 0x5000>;
  71                         clock-names = "clkout16";
  72                         clocks = <&fin_pll>;
  73                         #clock-cells = <1>;
  74                 };
  75
  76                 clock: clock-controller@10010000 {
  77                         compatible = "samsung,exynos5410-clock";
  78                         reg = <0x10010000 0x30000>;
  79                         #clock-cells = <1>;
  80                 };
  81
  82                 clock_audss: audss-clock-controller@3810000 {
  83                         compatible = "samsung,exynos5410-audss-clock";
  84                         reg = <0x03810000 0x0C>;
  85                         #clock-cells = <1>;
  86                         clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>;
  87                         clock-names = "pll_ref", "pll_in";
  88                 };
  89
  90                 tmu_cpu0: tmu@10060000 {
  91                         compatible = "samsung,exynos5420-tmu";
  92                         reg = <0x10060000 0x100>;
  93                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  94                         clocks = <&clock CLK_TMU>;
  95                         clock-names = "tmu_apbif";
  96                         #thermal-sensor-cells = <0>;
  97                 };
  98
  99                 tmu_cpu1: tmu@10064000 {
 100                         compatible = "samsung,exynos5420-tmu";
 101                         reg = <0x10064000 0x100>;
 102                         interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
 103                         clocks = <&clock CLK_TMU>;
 104                         clock-names = "tmu_apbif";
 105                         #thermal-sensor-cells = <0>;
 106                 };
 107
 108                 tmu_cpu2: tmu@10068000 {
 109                         compatible = "samsung,exynos5420-tmu";
 110                         reg = <0x10068000 0x100>;
 111                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 112                         clocks = <&clock CLK_TMU>;
 113                         clock-names = "tmu_apbif";
 114                         #thermal-sensor-cells = <0>;
 115                 };
 116
 117                 tmu_cpu3: tmu@1006c000 {
 118                         compatible = "samsung,exynos5420-tmu";
 119                         reg = <0x1006c000 0x100>;
 120                         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
 121                         clocks = <&clock CLK_TMU>;
 122                         clock-names = "tmu_apbif";
 123                         #thermal-sensor-cells = <0>;
 124                 };
 125
 126                 mmc_0: mmc@12200000 {
 127                         compatible = "samsung,exynos5250-dw-mshc";
 128                         reg = <0x12200000 0x1000>;
 129                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 130                         #address-cells = <1>;
 131                         #size-cells = <0>;
 132                         clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
 133                         clock-names = "biu", "ciu";
 134                         fifo-depth = <0x80>;
 135                         status = "disabled";
 136                 };
 137
 138                 mmc_1: mmc@12210000 {
 139                         compatible = "samsung,exynos5250-dw-mshc";
 140                         reg = <0x12210000 0x1000>;
 141                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 142                         #address-cells = <1>;
 143                         #size-cells = <0>;
 144                         clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
 145                         clock-names = "biu", "ciu";
 146                         fifo-depth = <0x80>;
 147                         status = "disabled";
 148                 };
 149
 150                 mmc_2: mmc@12220000 {
 151                         compatible = "samsung,exynos5250-dw-mshc";
 152                         reg = <0x12220000 0x1000>;
 153                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 154                         #address-cells = <1>;
 155                         #size-cells = <0>;
 156                         clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
 157                         clock-names = "biu", "ciu";
 158                         fifo-depth = <0x80>;
 159                         status = "disabled";
 160                 };
 161
 162                 pinctrl_0: pinctrl@13400000 {
 163                         compatible = "samsung,exynos5410-pinctrl";
 164                         reg = <0x13400000 0x1000>;
 165                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 166
 167                         wakeup-interrupt-controller {
 168                                 compatible = "samsung,exynos4210-wakeup-eint";
 169                                 interrupt-parent = <&gic>;
 170                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 171                         };
 172                 };
 173
 174                 pinctrl_1: pinctrl@14000000 {
 175                         compatible = "samsung,exynos5410-pinctrl";
 176                         reg = <0x14000000 0x1000>;
 177                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 178                 };
 179
 180                 pinctrl_2: pinctrl@10d10000 {
 181                         compatible = "samsung,exynos5410-pinctrl";
 182                         reg = <0x10d10000 0x1000>;
 183                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 184                 };
 185
 186                 pinctrl_3: pinctrl@3860000 {
 187                         compatible = "samsung,exynos5410-pinctrl";
 188                         reg = <0x03860000 0x1000>;
 189                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 190                 };
 191
 192                 pdma0: pdma@121a0000 {
 193                         compatible = "arm,pl330", "arm,primecell";
 194                         reg = <0x121a0000 0x1000>;
 195                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 196                         clocks = <&clock CLK_PDMA0>;
 197                         clock-names = "apb_pclk";
 198                         #dma-cells = <1>;
 199                         #dma-channels = <8>;
 200                         #dma-requests = <32>;
 201                 };
 202
 203                 pdma1: pdma@121b0000 {
 204                         compatible = "arm,pl330", "arm,primecell";
 205                         reg = <0x121b0000 0x1000>;
 206                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 207                         clocks = <&clock CLK_PDMA1>;
 208                         clock-names = "apb_pclk";
 209                         #dma-cells = <1>;
 210                         #dma-channels = <8>;
 211                         #dma-requests = <32>;
 212                 };
 213
 214                 audi2s0: i2s@3830000 {
 215                         compatible = "samsung,exynos5420-i2s";
 216                         reg = <0x03830000 0x100>;
 217                         dmas = <&pdma0 10>,
 218                                 <&pdma0 9>,
 219                                 <&pdma0 8>;
 220                         dma-names = "tx", "rx", "tx-sec";
 221                         clocks = <&clock_audss EXYNOS_I2S_BUS>,
 222                                 <&clock_audss EXYNOS_I2S_BUS>,
 223                                 <&clock_audss EXYNOS_SCLK_I2S>;
 224                         clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 225                         #clock-cells = <1>;
 226                         clock-output-names = "i2s_cdclk0";
 227                         #sound-dai-cells = <1>;
 228                         samsung,idma-addr = <0x03000000>;
 229                         pinctrl-names = "default";
 230                         pinctrl-0 = <&audi2s0_bus>;
 231                         status = "disabled";
 232                 };
 233         };
 234
 235         thermal-zones {
 236                 cpu0_thermal: cpu0-thermal {
 237                         thermal-sensors = <&tmu_cpu0>;
 238                         #include "exynos5420-trip-points.dtsi"
 239                 };
 240                 cpu1_thermal: cpu1-thermal {
 241                         thermal-sensors = <&tmu_cpu1>;
 242                         #include "exynos5420-trip-points.dtsi"
 243                 };
 244                 cpu2_thermal: cpu2-thermal {
 245                         thermal-sensors = <&tmu_cpu2>;
 246                         #include "exynos5420-trip-points.dtsi"
 247                 };
 248                 cpu3_thermal: cpu3-thermal {
 249                         thermal-sensors = <&tmu_cpu3>;
 250                         #include "exynos5420-trip-points.dtsi"
 251                 };
 252         };
 253 };
 254
 255 &adc {
 256         clocks = <&clock CLK_TSADC>;
 257         clock-names = "adc";
 258         samsung,syscon-phandle = <&pmu_system_controller>;
 259 };
 260
 261 &arm_a15_pmu {
 262         interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 263         status = "okay";
 264 };
 265
 266 &i2c_0 {
 267         clocks = <&clock CLK_I2C0>;
 268         clock-names = "i2c";
 269         pinctrl-names = "default";
 270         pinctrl-0 = <&i2c0_bus>;
 271 };
 272
 273 &i2c_1 {
 274         clocks = <&clock CLK_I2C1>;
 275         clock-names = "i2c";
 276         pinctrl-names = "default";
 277         pinctrl-0 = <&i2c1_bus>;
 278 };
 279
 280 &i2c_2 {
 281         clocks = <&clock CLK_I2C2>;
 282         clock-names = "i2c";
 283         pinctrl-names = "default";
 284         pinctrl-0 = <&i2c2_bus>;
 285 };
 286
 287 &i2c_3 {
 288         clocks = <&clock CLK_I2C3>;
 289         clock-names = "i2c";
 290         pinctrl-names = "default";
 291         pinctrl-0 = <&i2c3_bus>;
 292 };
 293
 294 &hsi2c_4 {
 295         clocks = <&clock CLK_USI0>;
 296         clock-names = "hsi2c";
 297         pinctrl-names = "default";
 298         pinctrl-0 = <&i2c4_hs_bus>;
 299 };
 300
 301 &hsi2c_5 {
 302         clocks = <&clock CLK_USI1>;
 303         clock-names = "hsi2c";
 304         pinctrl-names = "default";
 305         pinctrl-0 = <&i2c5_hs_bus>;
 306 };
 307
 308 &hsi2c_6 {
 309         clocks = <&clock CLK_USI2>;
 310         clock-names = "hsi2c";
 311         pinctrl-names = "default";
 312         pinctrl-0 = <&i2c6_hs_bus>;
 313 };
 314
 315 &hsi2c_7 {
 316         clocks = <&clock CLK_USI3>;
 317         clock-names = "hsi2c";
 318         pinctrl-names = "default";
 319         pinctrl-0 = <&i2c7_hs_bus>;
 320 };
 321
 322 &mct {
 323         clocks = <&fin_pll>, <&clock CLK_MCT>;
 324         clock-names = "fin_pll", "mct";
 325 };
 326
 327 &prng {
 328         clocks = <&clock CLK_SSS>;
 329         clock-names = "secss";
 330 };
 331
 332 &pwm {
 333         clocks = <&clock CLK_PWM>;
 334         clock-names = "timers";
 335 };
 336
 337 &rtc {
 338         clocks = <&clock CLK_RTC>;
 339         clock-names = "rtc";
 340         status = "disabled";
 341 };
 342
 343 &serial_0 {
 344         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 345         clock-names = "uart", "clk_uart_baud0";
 346         dmas = <&pdma0 13>, <&pdma0 14>;
 347         dma-names = "rx", "tx";
 348 };
 349
 350 &serial_1 {
 351         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 352         clock-names = "uart", "clk_uart_baud0";
 353         dmas = <&pdma1 15>, <&pdma1 16>;
 354         dma-names = "rx", "tx";
 355 };
 356
 357 &serial_2 {
 358         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 359         clock-names = "uart", "clk_uart_baud0";
 360         dmas = <&pdma0 15>, <&pdma0 16>;
 361         dma-names = "rx", "tx";
 362 };
 363
 364 &serial_3 {
 365         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
 366         clock-names = "uart", "clk_uart_baud0";
 367         dmas = <&pdma1 17>, <&pdma1 18>;
 368         dma-names = "rx", "tx";
 369 };
 370
 371 &sss {
 372         clocks = <&clock CLK_SSS>;
 373         clock-names = "secss";
 374 };
 375
 376 &sromc {
 377         #address-cells = <2>;
 378         #size-cells = <1>;
 379         ranges = <0 0 0x04000000 0x20000
 380                   1 0 0x05000000 0x20000
 381                   2 0 0x06000000 0x20000
 382                   3 0 0x07000000 0x20000>;
 383 };
 384
 385 &trng {
 386         clocks = <&clock CLK_SSS>;
 387         clock-names = "secss";
 388 };
 389
 390 &usbdrd3_0 {
 391         clocks = <&clock CLK_USBD300>;
 392         clock-names = "usbdrd30";
 393         pinctrl-names = "default";
 394         pinctrl-0 = <&usb3_0_oc>, <&usb3_0_vbusctrl>;
 395 };
 396
 397 &usbdrd_phy0 {
 398         clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
 399         clock-names = "phy", "ref";
 400         samsung,pmu-syscon = <&pmu_system_controller>;
 401 };
 402
 403 &usbdrd3_1 {
 404         clocks = <&clock CLK_USBD301>;
 405         clock-names = "usbdrd30";
 406         pinctrl-names = "default";
 407         pinctrl-0 = <&usb3_1_oc>, <&usb3_1_vbusctrl>;
 408 };
 409
 410 &usbdrd_dwc3_1 {
 411         interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
 412 };
 413
 414 &usbdrd_phy1 {
 415         clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
 416         clock-names = "phy", "ref";
 417         samsung,pmu-syscon = <&pmu_system_controller>;
 418 };
 419
 420 &usbhost1 {
 421         clocks = <&clock CLK_USBH20>;
 422         clock-names = "usbhost";
 423 };
 424
 425 &usbhost2 {
 426         clocks = <&clock CLK_USBH20>;
 427         clock-names = "usbhost";
 428 };
 429
 430 &usb2_phy {
 431         clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
 432         clock-names = "phy", "ref";
 433         samsung,sysreg-phandle = <&sysreg_system_controller>;
 434         samsung,pmureg-phandle = <&pmu_system_controller>;
 435 };
 436
 437 &watchdog {
 438         clocks = <&clock CLK_WDT>;
 439         clock-names = "watchdog";
 440         samsung,syscon-phandle = <&pmu_system_controller>;
 441 };
 442
 443 #include "exynos5410-pinctrl.dtsi"
 444 #include "exynos-syscon-restart.dtsi"