1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree file for the Storm Semiconductor SL93512R_BRD
4 * Gemini reference design, also initially called
5 * "Gemini324 EV-Board" before Storm acquired Storlink Semiconductor.
6 * The series were later acquired by Cortina Systems.
11 #include "gemini.dtsi"
12 #include <dt-bindings/input/input.h>
15 model = "Storlink Semiconductor Gemini324 EV-Board / Storm Semiconductor SL93512R_BRD";
16 compatible = "storlink,gemini324", "storm,sl93512r", "cortina,gemini";
21 /* 64 MB Samsung K4H511638B */
22 device_type = "memory";
23 reg = <0x00000000 0x4000000>;
27 bootargs = "console=ttyS0,19200n8 root=/dev/mtdblock3 rw rootfstype=squashfs,jffs2 rootwait";
32 compatible = "gpio-keys";
35 debounce-interval = <50>;
37 linux,code = <KEY_WPS_BUTTON>;
39 /* Conflicts with TVC and extended flash */
40 gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
44 debounce-interval = <50>;
46 linux,code = <KEY_SETUP>;
47 label = "factory reset";
48 /* Conflict with NAND flash */
49 gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
54 compatible = "gpio-leds";
56 label = "sq201:green:harddisk";
57 /* Conflict with LCD (no problem) */
58 gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
59 default-state = "off";
60 linux,default-trigger = "disk-activity";
63 label = "sq201:green:wireless";
64 /* Conflict with NAND flash CE0 (no problem) */
65 gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
67 linux,default-trigger = "heartbeat";
72 compatible = "virtual,mdio-gpio";
73 /* Uses MDC and MDIO */
74 gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
75 <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
79 /* This is a Marvell 88E1111 ethernet transciever */
80 phy0: ethernet-phy@1 {
86 compatible = "spi-gpio";
89 /* Check pin collisions */
90 gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
91 gpio-miso = <&gpio1 30 GPIO_ACTIVE_HIGH>;
92 gpio-mosi = <&gpio1 29 GPIO_ACTIVE_HIGH>;
93 cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
94 num-chipselects = <1>;
97 compatible = "vitesse,vsc7385";
99 /* Specified for 2.5 MHz or below */
100 spi-max-frequency = <2500000>;
105 #address-cells = <1>;
144 reg = <0x30000000 0x01000000>;
147 compatible = "redboot-fis";
148 /* Eraseblock at 0xfe0000 */
149 fis-index-block = <0x1fc>;
153 syscon: syscon@40000000 {
156 * gpio0agrp cover line 0, used by WPS button
157 * gpio0fgrp cover line 16 used by HD LED
158 * gpio0ggrp cover line 17, 18 used by wireless LAN LED and
159 * reset button OR USB ID select on 17 and USB VBUS select
160 * on 18. (Confusing.)
161 * gpio0igrp cover line 21, 22 used by MDIO for Marvell PHY
163 gpio0_default_pins: pinctrl-gpio0 {
166 groups = "gpio0agrp",
173 * gpio1dgrp cover lines used by SPI for
174 * the Vitesse chip (28-31)
176 gpio1_default_pins: pinctrl-gpio1 {
179 groups = "gpio1dgrp";
185 groups = "gmii_gmac0_grp", "gmii_gmac1_grp";
187 /* Control pad skew comes from sl_switch.c in the vendor code */
189 pins = "P10 GMAC1 TXC";
193 pins = "V11 GMAC1 TXEN";
197 pins = "T11 GMAC1 RXC";
201 pins = "U11 GMAC1 RXDV";
205 pins = "V7 GMAC0 TXC";
209 pins = "P8 GMAC0 TXEN";
210 skew-delay = <7>; /* 5 at another place? */
213 pins = "T8 GMAC0 RXC";
217 pins = "R8 GMAC0 RXDV";
221 /* The data lines all have default skew */
222 pins = "U8 GMAC0 RXD0", "V8 GMAC0 RXD1",
223 "P9 GMAC0 RXD2", "R9 GMAC0 RXD3",
224 "R11 GMAC1 RXD0", "P11 GMAC1 RXD1",
225 "V12 GMAC1 RXD2", "U12 GMAC1 RXD3",
226 "R10 GMAC1 TXD0", "T10 GMAC1 TXD1",
227 "U10 GMAC1 TXD2", "V10 GMAC1 TXD3";
230 /* Appears in sl351x_gmac.c in the vendor code */
232 pins = "U7 GMAC0 TXD0", "T7 GMAC0 TXD1",
233 "R7 GMAC0 TXD2", "P7 GMAC0 TXD3";
240 /* Both interfaces brought out on SATA connectors */
241 sata: sata@46000000 {
242 cortina,gemini-ata-muxmode = <0>;
243 cortina,gemini-enable-sata-bridge;
247 gpio0: gpio@4d000000 {
248 pinctrl-names = "default";
249 pinctrl-0 = <&gpio0_default_pins>;
252 gpio1: gpio@4e000000 {
253 pinctrl-names = "default";
254 pinctrl-0 = <&gpio1_default_pins>;
259 interrupt-map-mask = <0xf800 0 0 7>;
261 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
262 <0x4800 0 0 2 &pci_intc 1>,
263 <0x4800 0 0 3 &pci_intc 2>,
264 <0x4800 0 0 4 &pci_intc 3>,
265 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
266 <0x5000 0 0 2 &pci_intc 2>,
267 <0x5000 0 0 3 &pci_intc 3>,
268 <0x5000 0 0 4 &pci_intc 0>,
269 <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
270 <0x5800 0 0 2 &pci_intc 3>,
271 <0x5800 0 0 3 &pci_intc 0>,
272 <0x5800 0 0 4 &pci_intc 1>,
273 <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
274 <0x6000 0 0 2 &pci_intc 0>,
275 <0x6000 0 0 3 &pci_intc 1>,
276 <0x6000 0 0 4 &pci_intc 2>;
284 phy-handle = <&phy0>;