arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016 Eckelmann AG.
   4  * Copyright (C) 2013 Freescale Semiconductor, Inc.
   5  */
   6
   7 /dts-v1/;
   8
   9 #include <dt-bindings/gpio/gpio.h>
  10
  11 #include "imx6dl.dtsi"
  12
  13 / {
  14         model = "Eckelmann CI 4X10 Board";
  15         compatible = "eckelmann,imx6dl-ci4x10", "fsl,imx6dl";
  16
  17         chosen {
  18                 stdout-path = &uart3;
  19         };
  20
  21         memory@10000000 {
  22                 device_type = "memory";
  23                 reg = <0x10000000 0x40000000>;
  24         };
  25
  26         rmii_clk: clock-rmii {
  27                 /* This clock is provided by the phy (KSZ8091RNB) */
  28                 compatible = "fixed-clock";
  29                 #clock-cells = <0>;
  30                 clock-frequency = <50000000>;
  31         };
  32
  33         reg_usb_h1_vbus: regulator-usb-h1-vbus {
  34                 pinctrl-names = "default";
  35                 pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>;
  36                 compatible = "regulator-fixed";
  37                 regulator-name = "usb_h1_vbus";
  38                 regulator-min-microvolt = <5000000>;
  39                 regulator-max-microvolt = <5000000>;
  40                 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
  41                 enable-active-high;
  42         };
  43
  44         siox {
  45                 compatible = "eckelmann,siox-gpio";
  46                 pinctrl-names = "default";
  47                 pinctrl-0 = <&pinctrl_siox>;
  48                 din-gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>;
  49                 dout-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>;
  50                 dclk-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>;
  51                 dld-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>;
  52         };
  53 };
  54
  55 &can1 {
  56         pinctrl-names = "default";
  57         pinctrl-0 = <&pinctrl_flexcan1>;
  58         status = "okay";
  59 };
  60
  61 &can2 {
  62         pinctrl-names = "default";
  63         pinctrl-0 = <&pinctrl_flexcan2>;
  64         status = "okay";
  65 };
  66
  67 &ecspi2 {
  68         pinctrl-names = "default";
  69         pinctrl-0 = <&pinctrl_ecspi2>;
  70         cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
  71         status = "okay";
  72
  73         flash@0 {
  74                 compatible = "everspin,mr25h256";
  75                 reg = <0>;
  76                 spi-max-frequency = <15000000>;
  77         };
  78 };
  79
  80 &ecspi1 {
  81         pinctrl-names = "default";
  82         pinctrl-0 = <&pinctrl_ecspi1>;
  83         cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
  84         status = "okay";
  85
  86         tpm@0 {
  87                 compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
  88                 reg = <0>;
  89                 spi-max-frequency = <10000000>;
  90         };
  91 };
  92
  93 &gpio2 {
  94         gpio-line-names = "buzzer", "", "", "", "", "", "", "",
  95                           "", "", "", "", "", "", "", "",
  96                           "", "", "", "", "", "", "", "",
  97                           "", "", "", "", "", "", "", "";
  98 };
  99
 100 &gpio4 {
 101         gpio-line-names = "", "", "", "", "", "", "", "in2",
 102                           "prio2", "prio1", "aux", "", "", "", "", "",
 103                           "", "", "", "", "", "", "", "",
 104                           "", "", "", "", "", "", "", "";
 105 };
 106
 107 &gpio6 {
 108         gpio-line-names = "", "", "", "", "", "", "", "",
 109                           "", "", "", "", "", "", "", "in1",
 110                           "", "", "", "", "", "", "", "",
 111                           "", "", "", "", "", "", "", "";
 112 };
 113
 114 &i2c1 {
 115         pinctrl-names = "default";
 116         pinctrl-0 = <&pinctrl_i2c1>;
 117         status = "okay";
 118
 119         temperature-sensor@49 {
 120                 compatible = "ad,ad7414";
 121                 reg = <0x49>;
 122         };
 123
 124         rtc@51 {
 125                 compatible = "nxp,pcf2127";
 126                 reg = <0x51>;
 127         };
 128 };
 129
 130 &iomuxc {
 131         pinctrl-names = "default";
 132         pinctrl-0 = <&pinctrl_hog>;
 133
 134         pinctrl_hog: hog {
 135                 fsl,pins = <
 136                         MX6QDL_PAD_NANDF_D0__GPIO2_IO00         0x00000018 /* buzzer */
 137                         MX6QDL_PAD_KEY_COL1__GPIO4_IO08         0x00000018 /* OUT_1 */
 138                         MX6QDL_PAD_KEY_ROW1__GPIO4_IO09         0x00000018 /* OUT_2 */
 139                         MX6QDL_PAD_KEY_COL2__GPIO4_IO10         0x00000018 /* OUT_3 */
 140                         MX6QDL_PAD_NANDF_CS2__GPIO6_IO15        0x00000000 /* In1 */
 141                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x00000000 /* In2 */
 142                         MX6QDL_PAD_GPIO_9__GPIO1_IO09           0x00000018 /* unused watchdog pin */
 143                         MX6QDL_PAD_SD1_DAT2__GPIO1_IO19         0x00000018 /* unused watchdog pin */
 144
 145                 >;
 146         };
 147
 148         pinctrl_ecspi1: ecspi1grp {
 149                 fsl,pins = <
 150                         MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK       0x000100a0
 151                         MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI       0x000100a0
 152                         MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO       0x000100a0
 153                         MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25        0x000100a0
 154                 >;
 155         };
 156
 157         pinctrl_ecspi2: ecspi2grp {
 158                 fsl,pins = <
 159                         MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK     0x000100b1
 160                         MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI         0x000100b1
 161                         MX6QDL_PAD_EIM_OE__ECSPI2_MISO          0x000100b1
 162                         MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12      0x000100b1
 163                 >;
 164         };
 165
 166         pinctrl_enet: enetgrp {
 167                 fsl,pins = <
 168                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 169                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x0001b098
 170                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x0001b098
 171                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x0001b098
 172                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x0001b098
 173                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x0001b098
 174                         MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x0001b0b0
 175                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x0001b0b0
 176                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x0001b0b0
 177                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x0001b0b0
 178                         MX6QDL_PAD_SD1_CMD__GPIO1_IO18          0x00000018
 179                 >;
 180         };
 181
 182         pinctrl_flexcan1: flexcan1grp {
 183                 fsl,pins = <
 184                         MX6QDL_PAD_GPIO_7__FLEXCAN1_TX          0x0001b020
 185                         MX6QDL_PAD_GPIO_8__FLEXCAN1_RX          0x0001b0b0
 186                 >;
 187         };
 188
 189         pinctrl_flexcan2: flexcan2grp {
 190                 fsl,pins = <
 191                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX        0x0001b020
 192                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX        0x0001b0b0
 193                 >;
 194         };
 195
 196         pinctrl_i2c1: i2c1grp {
 197                 fsl,pins = <
 198                         /* without SION i2c doesn't detect bus busy */
 199                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b820
 200                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b820
 201                 >;
 202         };
 203
 204         pinctrl_pcie: pciegrp {
 205                 fsl,pins = <
 206                         MX6QDL_PAD_SD1_CLK__GPIO1_IO20          0x00000018
 207                 >;
 208         };
 209
 210         pinctrl_reg_usb_h1_vbus: reg_usb_h1_vbusgrp {
 211                 fsl,pins = <
 212                         MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x0001b0b0
 213                 >;
 214         };
 215
 216         pinctrl_siox: sioxgrp {
 217                 fsl,pins = <
 218                         MX6QDL_PAD_NANDF_CS0__GPIO6_IO11        0x0001b010      /* DIN */
 219                         MX6QDL_PAD_NANDF_ALE__GPIO6_IO08        0x0001b010      /* DOUT */
 220                         MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09       0x0001b010      /* DCLK */
 221                         MX6QDL_PAD_NANDF_RB0__GPIO6_IO10        0x0001b010      /* DLD */
 222                 >;
 223         };
 224
 225         pinctrl_uart1_dte: uart1grp {
 226                 fsl,pins = <
 227                         MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA    0x0001b010
 228                         MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA    0x0001b010
 229                         MX6QDL_PAD_EIM_D19__UART1_RTS_B         0x0001b010
 230                         MX6QDL_PAD_EIM_D20__UART1_CTS_B         0x0001b010
 231                         MX6QDL_PAD_EIM_D23__GPIO3_IO23          0x0001b010      /* DCD */
 232                         MX6QDL_PAD_EIM_D24__GPIO3_IO24          0x0001b010      /* DTR */
 233                         MX6QDL_PAD_EIM_D25__GPIO3_IO25          0x0001b010      /* DSR */
 234                 >;
 235         };
 236
 237         pinctrl_uart2_dte: uart2grp {
 238                 fsl,pins = <
 239                         MX6QDL_PAD_EIM_D27__UART2_TX_DATA       0x0001b010
 240                         MX6QDL_PAD_EIM_D26__UART2_RX_DATA       0x0001b010
 241                         MX6QDL_PAD_EIM_D28__UART2_RTS_B         0x0001b010
 242                         MX6QDL_PAD_EIM_D29__UART2_CTS_B         0x0001b010
 243                         MX6QDL_PAD_NANDF_D1__GPIO2_IO01         0x0001b010      /* DCD */
 244                         MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x0001b010      /* DTR */
 245                         MX6QDL_PAD_NANDF_CS3__GPIO6_IO16        0x0001b010      /* DSR */
 246                 >;
 247         };
 248
 249         pinctrl_uart3_dce: uart3grp {
 250                 fsl,pins = <
 251                         MX6QDL_PAD_SD4_CLK__UART3_RX_DATA       0x0001b010
 252                         MX6QDL_PAD_SD4_CMD__UART3_TX_DATA       0x0001b010
 253                 >;
 254         };
 255
 256         pinctrl_uart4_dce: uart4grp {
 257                 fsl,pins = <
 258                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x0001b010
 259                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x0001b010
 260                         MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03       0x0001b010
 261                 >;
 262         };
 263
 264         pinctrl_uart5_dce: uart5grp {
 265                 fsl,pins = <
 266                         MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA    0x0001b010
 267                         MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA    0x0001b010
 268                         MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05       0x0001b010      /* RTS */
 269                 >;
 270         };
 271
 272         pinctrl_usbh1: usbh1grp {
 273                 fsl,pins = <
 274                         MX6QDL_PAD_EIM_D30__USB_H1_OC           0x0001b0b0
 275                 >;
 276         };
 277
 278         pinctrl_usdhc3: usdhc3grp {
 279                 fsl,pins = <
 280                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x00017059
 281                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x00010059
 282                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x00017059
 283                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x00017059
 284                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x00017059
 285                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x00017059
 286                         MX6QDL_PAD_SD3_DAT4__SD3_DATA4          0x00017059
 287                         MX6QDL_PAD_SD3_DAT5__SD3_DATA5          0x00017059
 288                         MX6QDL_PAD_SD3_DAT6__SD3_DATA6          0x00017059
 289                         MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x00017059
 290                 >;
 291         };
 292 };
 293
 294 &fec {
 295         pinctrl-names = "default";
 296         pinctrl-0 = <&pinctrl_enet>;
 297         phy-mode = "rmii";
 298         phy-reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
 299         phy-handle = <&phy>;
 300         clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>;
 301         status = "okay";
 302
 303         mdio {
 304                 #address-cells = <1>;
 305                 #size-cells = <0>;
 306
 307                 phy: ethernet-phy@1 {
 308                         compatible = "ethernet-phy-ieee802.3-c22";
 309                         reg = <1>;
 310                 };
 311         };
 312 };
 313
 314 &pcie {
 315         pinctrl-names = "default";
 316         pinctrl-0 = <&pinctrl_pcie>;
 317         reset-gpio = <&gpio1 20 GPIO_ACTIVE_LOW>;
 318         status = "okay";
 319 };
 320
 321 &uart1 {
 322         pinctrl-names = "default";
 323         pinctrl-0 = <&pinctrl_uart1_dte>;
 324         uart-has-rtscts;
 325         fsl,dte-mode;
 326         dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
 327         dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
 328         dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
 329         status = "okay";
 330 };
 331
 332 &uart2 {
 333         pinctrl-names = "default";
 334         pinctrl-0 = <&pinctrl_uart2_dte>;
 335         uart-has-rtscts;
 336         fsl,dte-mode;
 337         dcd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
 338         dtr-gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
 339         dsr-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>;
 340         status = "okay";
 341 };
 342
 343 &uart3 {
 344         pinctrl-names = "default";
 345         pinctrl-0 = <&pinctrl_uart3_dce>;
 346         status = "okay";
 347 };
 348
 349 &uart4 {
 350         pinctrl-names = "default";
 351         pinctrl-0 = <&pinctrl_uart4_dce>;
 352         rts-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>;
 353         status = "okay";
 354 };
 355
 356 &uart5 {
 357         pinctrl-names = "default";
 358         pinctrl-0 = <&pinctrl_uart5_dce>;
 359         rts-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>;
 360         status = "okay";
 361 };
 362
 363 &usbh1 {
 364         pinctrl-names = "default";
 365         pinctrl-0 = <&pinctrl_usbh1>;
 366         vbus-supply = <&reg_usb_h1_vbus>;
 367         status = "okay";
 368 };
 369
 370 &usbotg {
 371         dr_mode = "peripheral";
 372         status = "okay";
 373 };
 374
 375 &usdhc3 {
 376         pinctrl-names = "default";
 377         pinctrl-0 = <&pinctrl_usdhc3>;
 378         bus-width = <8>;
 379         non-removable;
 380         status = "okay";
 381 };