arch/arm/boot/dts/imx6q-b850v3.dts

   1 /*
   2  * Copyright 2015 Timesys Corporation.
   3  * Copyright 2015 General Electric Company
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License
  12  *     version 2 as published by the Free Software Foundation.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 /dts-v1/;
  44
  45 #include "imx6q-bx50v3.dtsi"
  46
  47 / {
  48         model = "General Electric B850v3";
  49         compatible = "ge,imx6q-b850v3", "advantech,imx6q-ba16", "fsl,imx6q";
  50
  51         chosen {
  52                 stdout-path = &uart3;
  53         };
  54 };
  55
  56 &ldb {
  57         fsl,dual-channel;
  58         status = "okay";
  59
  60         lvds0: lvds-channel@0 {
  61                 fsl,data-mapping = "spwg";
  62                 fsl,data-width = <24>;
  63                 status = "okay";
  64
  65                 port@4 {
  66                         reg = <4>;
  67
  68                         lvds0_out: endpoint {
  69                                 remote-endpoint = <&stdp4028_in>;
  70                         };
  71                 };
  72         };
  73 };
  74
  75 &i2c2 {
  76         pca9547_ddc: mux@70 {
  77                 compatible = "nxp,pca9547";
  78                 reg = <0x70>;
  79                 #address-cells = <1>;
  80                 #size-cells = <0>;
  81
  82                 mux2_i2c1: i2c@0 {
  83                         #address-cells = <1>;
  84                         #size-cells = <0>;
  85                         reg = <0x0>;
  86                 };
  87
  88                 mux2_i2c2: i2c@1 {
  89                         #address-cells = <1>;
  90                         #size-cells = <0>;
  91                         reg = <0x1>;
  92                 };
  93
  94                 mux2_i2c3: i2c@2 {
  95                         #address-cells = <1>;
  96                         #size-cells = <0>;
  97                         reg = <0x2>;
  98                 };
  99
 100                 mux2_i2c4: i2c@3 {
 101                         #address-cells = <1>;
 102                         #size-cells = <0>;
 103                         reg = <0x3>;
 104                 };
 105
 106                 mux2_i2c5: i2c@4 {
 107                         #address-cells = <1>;
 108                         #size-cells = <0>;
 109                         reg = <0x4>;
 110                 };
 111
 112                 mux2_i2c6: i2c@5 {
 113                         #address-cells = <1>;
 114                         #size-cells = <0>;
 115                         reg = <0x5>;
 116                 };
 117
 118                 mux2_i2c7: i2c@6 {
 119                         #address-cells = <1>;
 120                         #size-cells = <0>;
 121                         reg = <0x6>;
 122                 };
 123
 124                 mux2_i2c8: i2c@7 {
 125                         #address-cells = <1>;
 126                         #size-cells = <0>;
 127                         reg = <0x7>;
 128                 };
 129         };
 130 };
 131
 132 &hdmi {
 133         ddc-i2c-bus = <&mux2_i2c1>;
 134 };
 135
 136 &mux1_i2c1 {
 137         ads7830@4a {
 138                 compatible = "ti,ads7830";
 139                 reg = <0x4a>;
 140         };
 141 };
 142
 143 &mux2_i2c2 {
 144         clock-frequency = <100000>;
 145
 146         stdp2690@72 {
 147                 compatible = "megachips,stdp2690-ge-b850v3-fw";
 148                 reg = <0x72>;
 149
 150                 ports {
 151                         #address-cells = <1>;
 152                         #size-cells = <0>;
 153
 154                         port@0 {
 155                                 reg = <0>;
 156
 157                                 stdp2690_in: endpoint {
 158                                         remote-endpoint = <&stdp4028_out>;
 159                                 };
 160                         };
 161
 162                         port@1 {
 163                                 reg = <1>;
 164
 165                                 stdp2690_out: endpoint {
 166                                         /* Connector for external display */
 167                                 };
 168                         };
 169                 };
 170         };
 171
 172         stdp4028@73 {
 173                 compatible = "megachips,stdp4028-ge-b850v3-fw";
 174                 reg = <0x73>;
 175                 interrupt-parent = <&gpio2>;
 176                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
 177
 178                 ports {
 179                         #address-cells = <1>;
 180                         #size-cells = <0>;
 181
 182                         port@0 {
 183                                 reg = <0>;
 184
 185                                 stdp4028_in: endpoint {
 186                                         remote-endpoint = <&lvds0_out>;
 187                                 };
 188                         };
 189
 190                         port@1 {
 191                                 reg = <1>;
 192
 193                                 stdp4028_out: endpoint {
 194                                         remote-endpoint = <&stdp2690_in>;
 195                                 };
 196                         };
 197                 };
 198         };
 199 };
 200
 201 &pca9539 {
 202         P10-hog {
 203                 gpio-hog;
 204                 gpios = <8 0>;
 205                 output-low;
 206                 line-name = "PCA9539-P10";
 207         };
 208
 209         P11-hog {
 210                 gpio-hog;
 211                 gpios = <9 0>;
 212                 output-low;
 213                 line-name = "PCA9539-P11";
 214         };
 215 };
 216
 217 &pci_root {
 218         /* PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch */
 219         bridge@1,0 {
 220                 compatible = "pci10b5,8605";
 221                 reg = <0x00010000 0 0 0 0>;
 222
 223                 #address-cells = <3>;
 224                 #size-cells = <2>;
 225                 #interrupt-cells = <1>;
 226
 227                 bridge@2,1 {
 228                         compatible = "pci10b5,8605";
 229                         reg = <0x00020800 0 0 0 0>;
 230
 231                         #address-cells = <3>;
 232                         #size-cells = <2>;
 233                         #interrupt-cells = <1>;
 234
 235                         /* Intel Corporation I210 Gigabit Network Connection */
 236                         ethernet@3,0 {
 237                                 compatible = "pci8086,1533";
 238                                 reg = <0x00030000 0 0 0 0>;
 239                         };
 240                 };
 241
 242                 bridge@2,2 {
 243                         compatible = "pci10b5,8605";
 244                         reg = <0x00021000 0 0 0 0>;
 245
 246                         #address-cells = <3>;
 247                         #size-cells = <2>;
 248                         #interrupt-cells = <1>;
 249
 250                         /* Intel Corporation I210 Gigabit Network Connection */
 251                         switch_nic: ethernet@4,0 {
 252                                 compatible = "pci8086,1533";
 253                                 reg = <0x00040000 0 0 0 0>;
 254                         };
 255                 };
 256         };
 257 };
 258
 259 &switch_ports {
 260         port@0 {
 261                 reg = <0>;
 262                 label = "eneport1";
 263                 phy-handle = <&switchphy0>;
 264         };
 265
 266         port@1 {
 267                 reg = <1>;
 268                 label = "eneport2";
 269                 phy-handle = <&switchphy1>;
 270         };
 271
 272         port@2 {
 273                 reg = <2>;
 274                 label = "enix";
 275                 phy-handle = <&switchphy2>;
 276         };
 277
 278         port@3 {
 279                 reg = <3>;
 280                 label = "enid";
 281                 phy-handle = <&switchphy3>;
 282         };
 283
 284         port@4 {
 285                 reg = <4>;
 286                 label = "cpu";
 287                 ethernet = <&switch_nic>;
 288                 phy-handle = <&switchphy4>;
 289         };
 290 };