arch/arm/boot/dts/imx6qdl-gw551x.dtsi

   1 /*
   2  * Copyright 2014 Gateworks Corporation
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of
  12  *     the License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include <dt-bindings/gpio/gpio.h>
  49 #include <dt-bindings/media/tda1997x.h>
  50 #include <dt-bindings/input/linux-event-codes.h>
  51 #include <dt-bindings/interrupt-controller/irq.h>
  52 #include <dt-bindings/sound/fsl-imx-audmux.h>
  53
  54 / {
  55         /* these are used by bootloader for disabling nodes */
  56         aliases {
  57                 led0 = &led0;
  58                 nand = &gpmi;
  59                 ssi0 = &ssi1;
  60                 usb0 = &usbh1;
  61                 usb1 = &usbotg;
  62         };
  63
  64         chosen {
  65                 bootargs = "console=ttymxc1,115200";
  66         };
  67
  68         gpio-keys {
  69                 compatible = "gpio-keys";
  70                 #address-cells = <1>;
  71                 #size-cells = <0>;
  72
  73                 user-pb {
  74                         label = "user_pb";
  75                         gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
  76                         linux,code = <BTN_0>;
  77                 };
  78
  79                 user-pb1x {
  80                         label = "user_pb1x";
  81                         linux,code = <BTN_1>;
  82                         interrupt-parent = <&gsc>;
  83                         interrupts = <0>;
  84                 };
  85
  86                 key-erased {
  87                         label = "key-erased";
  88                         linux,code = <BTN_2>;
  89                         interrupt-parent = <&gsc>;
  90                         interrupts = <1>;
  91                 };
  92
  93                 eeprom-wp {
  94                         label = "eeprom_wp";
  95                         linux,code = <BTN_3>;
  96                         interrupt-parent = <&gsc>;
  97                         interrupts = <2>;
  98                 };
  99
 100                 tamper {
 101                         label = "tamper";
 102                         linux,code = <BTN_4>;
 103                         interrupt-parent = <&gsc>;
 104                         interrupts = <5>;
 105                 };
 106
 107                 switch-hold {
 108                         label = "switch_hold";
 109                         linux,code = <BTN_5>;
 110                         interrupt-parent = <&gsc>;
 111                         interrupts = <7>;
 112                 };
 113         };
 114
 115         leds {
 116                 compatible = "gpio-leds";
 117                 pinctrl-names = "default";
 118                 pinctrl-0 = <&pinctrl_gpio_leds>;
 119
 120                 led0: user1 {
 121                         label = "user1";
 122                         gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
 123                         default-state = "on";
 124                         linux,default-trigger = "heartbeat";
 125                 };
 126         };
 127
 128         memory@10000000 {
 129                 device_type = "memory";
 130                 reg = <0x10000000 0x20000000>;
 131         };
 132
 133         reg_5p0v: regulator-5p0v {
 134                 compatible = "regulator-fixed";
 135                 regulator-name = "5P0V";
 136                 regulator-min-microvolt = <5000000>;
 137                 regulator-max-microvolt = <5000000>;
 138         };
 139
 140         reg_usb_h1_vbus: regulator-usb-h1-vbus {
 141                 compatible = "regulator-fixed";
 142                 regulator-name = "usb_h1_vbus";
 143                 regulator-min-microvolt = <5000000>;
 144                 regulator-max-microvolt = <5000000>;
 145         };
 146
 147         reg_usb_otg_vbus: regulator-usb-otg-vbus {
 148                 compatible = "regulator-fixed";
 149                 regulator-name = "usb_otg_vbus";
 150                 regulator-min-microvolt = <5000000>;
 151                 regulator-max-microvolt = <5000000>;
 152         };
 153
 154         sound-digital {
 155                 compatible = "simple-audio-card";
 156                 simple-audio-card,name = "tda1997x-audio";
 157                 simple-audio-card,format = "i2s";
 158                 simple-audio-card,bitclock-master = <&sound_codec>;
 159                 simple-audio-card,frame-master = <&sound_codec>;
 160
 161                 sound_cpu: simple-audio-card,cpu {
 162                         sound-dai = <&ssi1>;
 163                 };
 164
 165                 sound_codec: simple-audio-card,codec {
 166                         sound-dai = <&hdmi_receiver>;
 167                 };
 168         };
 169 };
 170
 171 &audmux {
 172         pinctrl-names = "default";
 173         pinctrl-0 = <&pinctrl_audmux>; /* AUD5<->tda1997x */
 174         status = "okay";
 175
 176         ssi1 {
 177                 fsl,audmux-port = <0>;
 178                 fsl,port-config = <
 179                         (IMX_AUDMUX_V2_PTCR_TFSDIR |
 180                         IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */
 181                         IMX_AUDMUX_V2_PTCR_TCLKDIR |
 182                         IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */
 183                         IMX_AUDMUX_V2_PTCR_SYN)
 184                         IMX_AUDMUX_V2_PDCR_RXDSEL(4)
 185                 >;
 186         };
 187
 188         aud5 {
 189                 fsl,audmux-port = <4>;
 190                 fsl,port-config = <
 191                         IMX_AUDMUX_V2_PTCR_SYN
 192                         IMX_AUDMUX_V2_PDCR_RXDSEL(0)>;
 193         };
 194 };
 195
 196 &can1 {
 197         pinctrl-names = "default";
 198         pinctrl-0 = <&pinctrl_flexcan1>;
 199         status = "okay";
 200 };
 201
 202 &gpmi {
 203         pinctrl-names = "default";
 204         pinctrl-0 = <&pinctrl_gpmi_nand>;
 205         status = "okay";
 206 };
 207
 208 &hdmi {
 209         ddc-i2c-bus = <&i2c3>;
 210         status = "okay";
 211 };
 212
 213 &i2c1 {
 214         clock-frequency = <100000>;
 215         pinctrl-names = "default";
 216         pinctrl-0 = <&pinctrl_i2c1>;
 217         status = "okay";
 218
 219         gsc: gsc@20 {
 220                 compatible = "gw,gsc";
 221                 reg = <0x20>;
 222                 interrupt-parent = <&gpio1>;
 223                 interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
 224                 interrupt-controller;
 225                 #interrupt-cells = <1>;
 226                 #size-cells = <0>;
 227
 228                 adc {
 229                         compatible = "gw,gsc-adc";
 230                         #address-cells = <1>;
 231                         #size-cells = <0>;
 232
 233                         channel@0 {
 234                                 gw,mode = <0>;
 235                                 reg = <0x00>;
 236                                 label = "temp";
 237                         };
 238
 239                         channel@2 {
 240                                 gw,mode = <1>;
 241                                 reg = <0x02>;
 242                                 label = "vdd_vin";
 243                         };
 244
 245                         channel@5 {
 246                                 gw,mode = <1>;
 247                                 reg = <0x05>;
 248                                 label = "vdd_3p3";
 249                         };
 250
 251                         channel@8 {
 252                                 gw,mode = <1>;
 253                                 reg = <0x08>;
 254                                 label = "vdd_bat";
 255                         };
 256
 257                         channel@b {
 258                                 gw,mode = <1>;
 259                                 reg = <0x0b>;
 260                                 label = "vdd_5p0";
 261                         };
 262
 263                         channel@e {
 264                                 gw,mode = <1>;
 265                                 reg = <0xe>;
 266                                 label = "vdd_arm";
 267                         };
 268
 269                         channel@11 {
 270                                 gw,mode = <1>;
 271                                 reg = <0x11>;
 272                                 label = "vdd_soc";
 273                         };
 274
 275                         channel@14 {
 276                                 gw,mode = <1>;
 277                                 reg = <0x14>;
 278                                 label = "vdd_3p0";
 279                         };
 280
 281                         channel@17 {
 282                                 gw,mode = <1>;
 283                                 reg = <0x17>;
 284                                 label = "vdd_1p5";
 285                         };
 286
 287                         channel@1d {
 288                                 gw,mode = <1>;
 289                                 reg = <0x1d>;
 290                                 label = "vdd_1p8a";
 291                         };
 292
 293                         channel@20 {
 294                                 gw,mode = <1>;
 295                                 reg = <0x20>;
 296                                 label = "vdd_1p0b";
 297                         };
 298                 };
 299         };
 300
 301         gsc_gpio: gpio@23 {
 302                 compatible = "nxp,pca9555";
 303                 reg = <0x23>;
 304                 gpio-controller;
 305                 #gpio-cells = <2>;
 306                 interrupt-parent = <&gsc>;
 307                 interrupts = <4>;
 308         };
 309
 310         eeprom1: eeprom@50 {
 311                 compatible = "atmel,24c02";
 312                 reg = <0x50>;
 313                 pagesize = <16>;
 314         };
 315
 316         eeprom2: eeprom@51 {
 317                 compatible = "atmel,24c02";
 318                 reg = <0x51>;
 319                 pagesize = <16>;
 320         };
 321
 322         eeprom3: eeprom@52 {
 323                 compatible = "atmel,24c02";
 324                 reg = <0x52>;
 325                 pagesize = <16>;
 326         };
 327
 328         eeprom4: eeprom@53 {
 329                 compatible = "atmel,24c02";
 330                 reg = <0x53>;
 331                 pagesize = <16>;
 332         };
 333
 334         rtc: ds1672@68 {
 335                 compatible = "dallas,ds1672";
 336                 reg = <0x68>;
 337         };
 338 };
 339
 340 &i2c2 {
 341         clock-frequency = <100000>;
 342         pinctrl-names = "default";
 343         pinctrl-0 = <&pinctrl_i2c2>;
 344         status = "okay";
 345
 346         ltc3676: pmic@3c {
 347                 compatible = "lltc,ltc3676";
 348                 reg = <0x3c>;
 349                 pinctrl-names = "default";
 350                 pinctrl-0 = <&pinctrl_pmic>;
 351                 interrupt-parent = <&gpio1>;
 352                 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
 353
 354                 regulators {
 355                         /* VDD_SOC (1+R1/R2 = 1.635) */
 356                         reg_vdd_soc: sw1 {
 357                                 regulator-name = "vddsoc";
 358                                 regulator-min-microvolt = <674400>;
 359                                 regulator-max-microvolt = <1308000>;
 360                                 lltc,fb-voltage-divider = <127000 200000>;
 361                                 regulator-ramp-delay = <7000>;
 362                                 regulator-boot-on;
 363                                 regulator-always-on;
 364                         };
 365
 366                         /* VDD_DDR (1+R1/R2 = 2.105) */
 367                         reg_vdd_ddr: sw2 {
 368                                 regulator-name = "vddddr";
 369                                 regulator-min-microvolt = <868310>;
 370                                 regulator-max-microvolt = <1684000>;
 371                                 lltc,fb-voltage-divider = <221000 200000>;
 372                                 regulator-ramp-delay = <7000>;
 373                                 regulator-boot-on;
 374                                 regulator-always-on;
 375                         };
 376
 377                         /* VDD_ARM (1+R1/R2 = 1.635) */
 378                         reg_vdd_arm: sw3 {
 379                                 regulator-name = "vddarm";
 380                                 regulator-min-microvolt = <674400>;
 381                                 regulator-max-microvolt = <1308000>;
 382                                 lltc,fb-voltage-divider = <127000 200000>;
 383                                 regulator-ramp-delay = <7000>;
 384                                 regulator-boot-on;
 385                                 regulator-always-on;
 386                         };
 387
 388                         /* VDD_3P3 (1+R1/R2 = 1.281) */
 389                         reg_3p3: sw4 {
 390                                 regulator-name = "vdd3p3";
 391                                 regulator-min-microvolt = <1880000>;
 392                                 regulator-max-microvolt = <3647000>;
 393                                 lltc,fb-voltage-divider = <200000 56200>;
 394                                 regulator-ramp-delay = <7000>;
 395                                 regulator-boot-on;
 396                                 regulator-always-on;
 397                         };
 398
 399                         /* VDD_1P8a (1+R1/R2 = 2.505): HDMI In core */
 400                         reg_1p8a: ldo2 {
 401                                 regulator-name = "vdd1p8a";
 402                                 regulator-min-microvolt = <1816125>;
 403                                 regulator-max-microvolt = <1816125>;
 404                                 lltc,fb-voltage-divider = <301000 200000>;
 405                                 regulator-boot-on;
 406                                 regulator-always-on;
 407                         };
 408
 409                         /* VDD_1P8b: HDMI In analog */
 410                         reg_1p8b: ldo3 {
 411                                 regulator-name = "vdd1p8b";
 412                                 regulator-min-microvolt = <1800000>;
 413                                 regulator-max-microvolt = <1800000>;
 414                                 regulator-boot-on;
 415                         };
 416
 417                         /* VDD_HIGH (1+R1/R2 = 4.17) */
 418                         reg_3p0: ldo4 {
 419                                 regulator-name = "vdd3p0";
 420                                 regulator-min-microvolt = <3023250>;
 421                                 regulator-max-microvolt = <3023250>;
 422                                 lltc,fb-voltage-divider = <634000 200000>;
 423                                 regulator-boot-on;
 424                                 regulator-always-on;
 425                         };
 426                 };
 427         };
 428 };
 429
 430 &i2c3 {
 431         clock-frequency = <100000>;
 432         pinctrl-names = "default";
 433         pinctrl-0 = <&pinctrl_i2c3>;
 434         status = "okay";
 435
 436         gpio_exp: pca9555@24 {
 437                 compatible = "nxp,pca9555";
 438                 reg = <0x24>;
 439                 gpio-controller;
 440                 #gpio-cells = <2>;
 441         };
 442
 443         hdmi_receiver: hdmi-receiver@48 {
 444                 compatible = "nxp,tda19971";
 445                 pinctrl-names = "default";
 446                 pinctrl-0 = <&pinctrl_tda1997x>;
 447                 reg = <0x48>;
 448                 interrupt-parent = <&gpio1>;
 449                 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
 450                 DOVDD-supply = <&reg_3p3>;
 451                 AVDD-supply = <&reg_1p8b>;
 452                 DVDD-supply = <&reg_1p8a>;
 453                 #sound-dai-cells = <0>;
 454                 nxp,audout-format = "i2s";
 455                 nxp,audout-layout = <0>;
 456                 nxp,audout-width = <16>;
 457                 nxp,audout-mclk-fs = <128>;
 458                 /*
 459                  * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
 460                  * and Y[11:4] across 16bits in the same cycle
 461                  * which we map to VP[15:08]<->CSI_DATA[19:12]
 462                  */
 463                 nxp,vidout-portcfg =
 464                         /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/
 465                         < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
 466                         /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/
 467                         < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
 468                         /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/
 469                         < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
 470                         /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/
 471                         < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
 472
 473                 port {
 474                         tda1997x_to_ipu1_csi0_mux: endpoint {
 475                                 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
 476                                 bus-width = <16>;
 477                                 hsync-active = <1>;
 478                                 vsync-active = <1>;
 479                                 data-active = <1>;
 480                         };
 481                 };
 482         };
 483 };
 484
 485 &ipu1_csi0_from_ipu1_csi0_mux {
 486         bus-width = <16>;
 487 };
 488
 489 &ipu1_csi0_mux_from_parallel_sensor {
 490         remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>;
 491         bus-width = <16>;
 492 };
 493
 494 &ipu1_csi0 {
 495         pinctrl-names = "default";
 496         pinctrl-0 = <&pinctrl_ipu1_csi0>;
 497 };
 498
 499 &pcie {
 500         pinctrl-names = "default";
 501         pinctrl-0 = <&pinctrl_pcie>;
 502         reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
 503         status = "okay";
 504 };
 505
 506 &pwm2 {
 507         pinctrl-names = "default";
 508         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 509         status = "disabled";
 510 };
 511
 512 &pwm3 {
 513         pinctrl-names = "default";
 514         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 515         status = "disabled";
 516 };
 517
 518 &ssi1 {
 519         status = "okay";
 520 };
 521
 522 &uart2 {
 523         pinctrl-names = "default";
 524         pinctrl-0 = <&pinctrl_uart2>;
 525         status = "okay";
 526 };
 527
 528 &uart3 {
 529         pinctrl-names = "default";
 530         pinctrl-0 = <&pinctrl_uart3>;
 531         status = "okay";
 532 };
 533
 534 &usbotg {
 535         vbus-supply = <&reg_usb_otg_vbus>;
 536         pinctrl-names = "default";
 537         pinctrl-0 = <&pinctrl_usbotg>;
 538         disable-over-current;
 539         status = "okay";
 540 };
 541
 542 &usbh1 {
 543         vbus-supply = <&reg_usb_h1_vbus>;
 544         status = "okay";
 545 };
 546
 547 &wdog1 {
 548         pinctrl-names = "default";
 549         pinctrl-0 = <&pinctrl_wdog>;
 550         fsl,ext-reset-output;
 551 };
 552
 553 &iomuxc {
 554         pinctrl_audmux: audmuxgrp {
 555                 fsl,pins = <
 556                         MX6QDL_PAD_DISP0_DAT19__AUD5_RXD        0x130b0
 557                         MX6QDL_PAD_DISP0_DAT14__AUD5_RXC        0x130b0
 558                         MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS       0x130b0
 559                 >;
 560         };
 561
 562         pinctrl_flexcan1: flexcan1grp {
 563                 fsl,pins = <
 564                         MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b1
 565                         MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b1
 566                         MX6QDL_PAD_GPIO_9__GPIO1_IO09           0x4001b0b0 /* CAN_STBY */
 567                 >;
 568         };
 569
 570         pinctrl_gpio_leds: gpioledsgrp {
 571                 fsl,pins = <
 572                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07   0x1b0b0
 573                 >;
 574         };
 575
 576         pinctrl_gpmi_nand: gpminandgrp {
 577                 fsl,pins = <
 578                         MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 579                         MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 580                         MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 581                         MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 582                         MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 583                         MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 584                         MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 585                         MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 586                         MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 587                         MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 588                         MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 589                         MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 590                         MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 591                         MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 592                         MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 593                 >;
 594         };
 595
 596         pinctrl_i2c1: i2c1grp {
 597                 fsl,pins = <
 598                         MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 599                         MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 600                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0xb0b1
 601                 >;
 602         };
 603
 604         pinctrl_i2c2: i2c2grp {
 605                 fsl,pins = <
 606                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 607                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 608                 >;
 609         };
 610
 611         pinctrl_i2c3: i2c3grp {
 612                 fsl,pins = <
 613                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 614                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 615                 >;
 616         };
 617
 618         pinctrl_ipu1_csi0: ipu1_csi0grp {
 619                 fsl,pins = <
 620                         MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04          0x1b0b0
 621                         MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05          0x1b0b0
 622                         MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06          0x1b0b0
 623                         MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07          0x1b0b0
 624                         MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08          0x1b0b0
 625                         MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09          0x1b0b0
 626                         MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10         0x1b0b0
 627                         MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11         0x1b0b0
 628                         MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12         0x1b0b0
 629                         MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13         0x1b0b0
 630                         MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14         0x1b0b0
 631                         MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15         0x1b0b0
 632                         MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16         0x1b0b0
 633                         MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17         0x1b0b0
 634                         MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18         0x1b0b0
 635                         MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19         0x1b0b0
 636                         MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC           0x1b0b0
 637                         MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK        0x1b0b0
 638                         MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC          0x1b0b0
 639                 >;
 640         };
 641
 642         pinctrl_pcie: pciegrp {
 643                 fsl,pins = <
 644                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x1b0b0 /* PCIE RST */
 645                 >;
 646         };
 647
 648         pinctrl_pmic: pmicgrp {
 649                 fsl,pins = <
 650                         MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x0001b0b0 /* PMIC_IRQ# */
 651                 >;
 652         };
 653
 654         pinctrl_pwm2: pwm2grp {
 655                 fsl,pins = <
 656                         MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 657                 >;
 658         };
 659
 660         pinctrl_pwm3: pwm3grp {
 661                 fsl,pins = <
 662                         MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 663                 >;
 664         };
 665
 666         pinctrl_tda1997x: tda1997xgrp {
 667                 fsl,pins = <
 668                         MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x1b0b0
 669                 >;
 670         };
 671
 672         pinctrl_uart2: uart2grp {
 673                 fsl,pins = <
 674                         MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 675                         MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 676                 >;
 677         };
 678
 679         pinctrl_uart3: uart3grp {
 680                 fsl,pins = <
 681                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 682                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 683                 >;
 684         };
 685
 686         pinctrl_usbotg: usbotggrp {
 687                 fsl,pins = <
 688                         MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 689                 >;
 690         };
 691
 692         pinctrl_wdog: wdoggrp {
 693                 fsl,pins = <
 694                         MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 695                 >;
 696         };
 697 };