arch/arm/boot/dts/imx6ul-14x14-evk.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright (C) 2015 Freescale Semiconductor, Inc.
   4
   5 / {
   6         chosen {
   7                 stdout-path = &uart1;
   8         };
   9
  10         memory@80000000 {
  11                 device_type = "memory";
  12                 reg = <0x80000000 0x20000000>;
  13         };
  14
  15         backlight_display: backlight-display {
  16                 compatible = "pwm-backlight";
  17                 pwms = <&pwm1 0 5000000>;
  18                 brightness-levels = <0 4 8 16 32 64 128 255>;
  19                 default-brightness-level = <6>;
  20                 status = "okay";
  21         };
  22
  23
  24         reg_sd1_vmmc: regulator-sd1-vmmc {
  25                 compatible = "regulator-fixed";
  26                 regulator-name = "VSD_3V3";
  27                 regulator-min-microvolt = <3300000>;
  28                 regulator-max-microvolt = <3300000>;
  29                 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  30                 enable-active-high;
  31         };
  32
  33         reg_peri_3v3: regulator-peri-3v3 {
  34                 compatible = "regulator-fixed";
  35                 pinctrl-names = "default";
  36                 pinctrl-0 = <&pinctrl_peri_3v3>;
  37                 regulator-name = "VPERI_3V3";
  38                 regulator-min-microvolt = <3300000>;
  39                 regulator-max-microvolt = <3300000>;
  40                 gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
  41                 /*
  42                  * If you want to want to make this dynamic please
  43                  * check schematics and test all affected peripherals:
  44                  *
  45                  * - sensors
  46                  * - ethernet phy
  47                  * - can
  48                  * - bluetooth
  49                  * - wm8960 audio codec
  50                  * - ov5640 camera
  51                  */
  52                 regulator-always-on;
  53         };
  54
  55         reg_can_3v3: regulator-can-3v3 {
  56                 compatible = "regulator-fixed";
  57                 regulator-name = "can-3v3";
  58                 regulator-min-microvolt = <3300000>;
  59                 regulator-max-microvolt = <3300000>;
  60                 gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
  61         };
  62
  63         sound {
  64                 compatible = "simple-audio-card";
  65                 simple-audio-card,name = "mx6ul-wm8960";
  66                 simple-audio-card,format = "i2s";
  67                 simple-audio-card,bitclock-master = <&dailink_master>;
  68                 simple-audio-card,frame-master = <&dailink_master>;
  69                 simple-audio-card,widgets =
  70                         "Microphone", "Mic Jack",
  71                         "Line", "Line In",
  72                         "Line", "Line Out",
  73                         "Speaker", "Speaker",
  74                         "Headphone", "Headphone Jack";
  75                 simple-audio-card,routing =
  76                         "Headphone Jack", "HP_L",
  77                         "Headphone Jack", "HP_R",
  78                         "Speaker", "SPK_LP",
  79                         "Speaker", "SPK_LN",
  80                         "Speaker", "SPK_RP",
  81                         "Speaker", "SPK_RN",
  82                         "LINPUT1", "Mic Jack",
  83                         "LINPUT3", "Mic Jack",
  84                         "RINPUT1", "Mic Jack",
  85                         "RINPUT2", "Mic Jack";
  86
  87                 simple-audio-card,cpu {
  88                         sound-dai = <&sai2>;
  89                 };
  90
  91                 dailink_master: simple-audio-card,codec {
  92                         sound-dai = <&codec>;
  93                         clocks = <&clks IMX6UL_CLK_SAI2>;
  94                 };
  95         };
  96
  97         spi4 {
  98                 compatible = "spi-gpio";
  99                 pinctrl-names = "default";
 100                 pinctrl-0 = <&pinctrl_spi4>;
 101                 status = "okay";
 102                 gpio-sck = <&gpio5 11 0>;
 103                 gpio-mosi = <&gpio5 10 0>;
 104                 cs-gpios = <&gpio5 7 0>;
 105                 num-chipselects = <1>;
 106                 #address-cells = <1>;
 107                 #size-cells = <0>;
 108
 109                 gpio_spi: gpio@0 {
 110                         compatible = "fairchild,74hc595";
 111                         gpio-controller;
 112                         #gpio-cells = <2>;
 113                         reg = <0>;
 114                         registers-number = <1>;
 115                         spi-max-frequency = <100000>;
 116                 };
 117         };
 118
 119         panel {
 120                 compatible = "innolux,at043tn24";
 121                 backlight = <&backlight_display>;
 122
 123                 port {
 124                         panel_in: endpoint {
 125                                 remote-endpoint = <&display_out>;
 126                         };
 127                 };
 128         };
 129 };
 130
 131 &clks {
 132         assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
 133         assigned-clock-rates = <786432000>;
 134 };
 135
 136 &i2c2 {
 137         clock-frequency = <100000>;
 138         pinctrl-names = "default";
 139         pinctrl-0 = <&pinctrl_i2c2>;
 140         status = "okay";
 141
 142         codec: wm8960@1a {
 143                 #sound-dai-cells = <0>;
 144                 compatible = "wlf,wm8960";
 145                 reg = <0x1a>;
 146                 wlf,shared-lrclk;
 147         };
 148 };
 149
 150 &fec1 {
 151         pinctrl-names = "default";
 152         pinctrl-0 = <&pinctrl_enet1>;
 153         phy-mode = "rmii";
 154         phy-handle = <&ethphy0>;
 155         phy-supply = <&reg_peri_3v3>;
 156         status = "okay";
 157 };
 158
 159 &fec2 {
 160         pinctrl-names = "default";
 161         pinctrl-0 = <&pinctrl_enet2>;
 162         phy-mode = "rmii";
 163         phy-handle = <&ethphy1>;
 164         phy-supply = <&reg_peri_3v3>;
 165         status = "okay";
 166
 167         mdio {
 168                 #address-cells = <1>;
 169                 #size-cells = <0>;
 170
 171                 ethphy0: ethernet-phy@2 {
 172                         reg = <2>;
 173                         micrel,led-mode = <1>;
 174                         clocks = <&clks IMX6UL_CLK_ENET_REF>;
 175                         clock-names = "rmii-ref";
 176                 };
 177
 178                 ethphy1: ethernet-phy@1 {
 179                         reg = <1>;
 180                         micrel,led-mode = <1>;
 181                         clocks = <&clks IMX6UL_CLK_ENET2_REF>;
 182                         clock-names = "rmii-ref";
 183                 };
 184         };
 185 };
 186
 187 &can1 {
 188         pinctrl-names = "default";
 189         pinctrl-0 = <&pinctrl_flexcan1>;
 190         xceiver-supply = <&reg_can_3v3>;
 191         status = "okay";
 192 };
 193
 194 &can2 {
 195         pinctrl-names = "default";
 196         pinctrl-0 = <&pinctrl_flexcan2>;
 197         xceiver-supply = <&reg_can_3v3>;
 198         status = "okay";
 199 };
 200
 201 &i2c1 {
 202         clock-frequency = <100000>;
 203         pinctrl-names = "default";
 204         pinctrl-0 = <&pinctrl_i2c1>;
 205         status = "okay";
 206
 207         magnetometer@e {
 208                 compatible = "fsl,mag3110";
 209                 reg = <0x0e>;
 210                 vdd-supply = <&reg_peri_3v3>;
 211                 vddio-supply = <&reg_peri_3v3>;
 212         };
 213 };
 214
 215 &lcdif {
 216         assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
 217         assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
 218         pinctrl-names = "default";
 219         pinctrl-0 = <&pinctrl_lcdif_dat
 220                      &pinctrl_lcdif_ctrl>;
 221         status = "okay";
 222
 223         port {
 224                 display_out: endpoint {
 225                         remote-endpoint = <&panel_in>;
 226                 };
 227         };
 228 };
 229
 230 &pwm1 {
 231         #pwm-cells = <2>;
 232         pinctrl-names = "default";
 233         pinctrl-0 = <&pinctrl_pwm1>;
 234         status = "okay";
 235 };
 236
 237 &qspi {
 238         pinctrl-names = "default";
 239         pinctrl-0 = <&pinctrl_qspi>;
 240         status = "okay";
 241
 242         flash0: n25q256a@0 {
 243                 #address-cells = <1>;
 244                 #size-cells = <1>;
 245                 compatible = "micron,n25q256a", "jedec,spi-nor";
 246                 spi-max-frequency = <29000000>;
 247                 spi-rx-bus-width = <4>;
 248                 spi-tx-bus-width = <4>;
 249                 reg = <0>;
 250         };
 251 };
 252
 253 &sai2 {
 254         pinctrl-names = "default";
 255         pinctrl-0 = <&pinctrl_sai2>;
 256         assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
 257                           <&clks IMX6UL_CLK_SAI2>;
 258         assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
 259         assigned-clock-rates = <0>, <12288000>;
 260         fsl,sai-mclk-direction-output;
 261         status = "okay";
 262 };
 263
 264 &snvs_poweroff {
 265         status = "okay";
 266 };
 267
 268 &snvs_pwrkey {
 269         status = "okay";
 270 };
 271
 272 &tsc {
 273         pinctrl-names = "default";
 274         pinctrl-0 = <&pinctrl_tsc>;
 275         xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
 276         measure-delay-time = <0xffff>;
 277         pre-charge-time = <0xfff>;
 278         status = "okay";
 279 };
 280
 281 &uart1 {
 282         pinctrl-names = "default";
 283         pinctrl-0 = <&pinctrl_uart1>;
 284         status = "okay";
 285 };
 286
 287 &uart2 {
 288         pinctrl-names = "default";
 289         pinctrl-0 = <&pinctrl_uart2>;
 290         uart-has-rtscts;
 291         status = "okay";
 292 };
 293
 294 &usbotg1 {
 295         dr_mode = "otg";
 296         pinctrl-names = "default";
 297         pinctrl-0 = <&pinctrl_usb_otg1>;
 298         status = "okay";
 299 };
 300
 301 &usbotg2 {
 302         dr_mode = "host";
 303         disable-over-current;
 304         status = "okay";
 305 };
 306
 307 &usbphy1 {
 308         fsl,tx-d-cal = <106>;
 309 };
 310
 311 &usbphy2 {
 312         fsl,tx-d-cal = <106>;
 313 };
 314
 315 &usdhc1 {
 316         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 317         pinctrl-0 = <&pinctrl_usdhc1>;
 318         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 319         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 320         cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
 321         keep-power-in-suspend;
 322         wakeup-source;
 323         vmmc-supply = <&reg_sd1_vmmc>;
 324         status = "okay";
 325 };
 326
 327 &usdhc2 {
 328         pinctrl-names = "default";
 329         pinctrl-0 = <&pinctrl_usdhc2>;
 330         no-1-8-v;
 331         broken-cd;
 332         keep-power-in-suspend;
 333         wakeup-source;
 334         status = "okay";
 335 };
 336
 337 &wdog1 {
 338         pinctrl-names = "default";
 339         pinctrl-0 = <&pinctrl_wdog>;
 340         fsl,ext-reset-output;
 341 };
 342
 343 &iomuxc {
 344         pinctrl-names = "default";
 345
 346         pinctrl_csi1: csi1grp {
 347                 fsl,pins = <
 348                         MX6UL_PAD_CSI_MCLK__CSI_MCLK            0x1b088
 349                         MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK        0x1b088
 350                         MX6UL_PAD_CSI_VSYNC__CSI_VSYNC          0x1b088
 351                         MX6UL_PAD_CSI_HSYNC__CSI_HSYNC          0x1b088
 352                         MX6UL_PAD_CSI_DATA00__CSI_DATA02        0x1b088
 353                         MX6UL_PAD_CSI_DATA01__CSI_DATA03        0x1b088
 354                         MX6UL_PAD_CSI_DATA02__CSI_DATA04        0x1b088
 355                         MX6UL_PAD_CSI_DATA03__CSI_DATA05        0x1b088
 356                         MX6UL_PAD_CSI_DATA04__CSI_DATA06        0x1b088
 357                         MX6UL_PAD_CSI_DATA05__CSI_DATA07        0x1b088
 358                         MX6UL_PAD_CSI_DATA06__CSI_DATA08        0x1b088
 359                         MX6UL_PAD_CSI_DATA07__CSI_DATA09        0x1b088
 360                 >;
 361         };
 362
 363         pinctrl_enet1: enet1grp {
 364                 fsl,pins = <
 365                         MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
 366                         MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
 367                         MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
 368                         MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
 369                         MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
 370                         MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
 371                         MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
 372                         MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
 373                 >;
 374         };
 375
 376         pinctrl_enet2: enet2grp {
 377                 fsl,pins = <
 378                         MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x1b0b0
 379                         MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
 380                         MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN      0x1b0b0
 381                         MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER      0x1b0b0
 382                         MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
 383                         MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
 384                         MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN      0x1b0b0
 385                         MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
 386                         MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
 387                         MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2  0x4001b031
 388                 >;
 389         };
 390
 391         pinctrl_flexcan1: flexcan1grp{
 392                 fsl,pins = <
 393                         MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX      0x1b020
 394                         MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX      0x1b020
 395                 >;
 396         };
 397
 398         pinctrl_flexcan2: flexcan2grp{
 399                 fsl,pins = <
 400                         MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX      0x1b020
 401                         MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX      0x1b020
 402                 >;
 403         };
 404
 405         pinctrl_i2c1: i2c1grp {
 406                 fsl,pins = <
 407                         MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
 408                         MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
 409                 >;
 410         };
 411
 412         pinctrl_i2c2: i2c2grp {
 413                 fsl,pins = <
 414                         MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
 415                         MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
 416                 >;
 417         };
 418
 419         pinctrl_lcdif_dat: lcdifdatgrp {
 420                 fsl,pins = <
 421                         MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
 422                         MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
 423                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
 424                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
 425                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
 426                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
 427                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
 428                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
 429                         MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
 430                         MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
 431                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
 432                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
 433                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
 434                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
 435                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
 436                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
 437                         MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
 438                         MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
 439                         MX6UL_PAD_LCD_DATA18__LCDIF_DATA18  0x79
 440                         MX6UL_PAD_LCD_DATA19__LCDIF_DATA19  0x79
 441                         MX6UL_PAD_LCD_DATA20__LCDIF_DATA20  0x79
 442                         MX6UL_PAD_LCD_DATA21__LCDIF_DATA21  0x79
 443                         MX6UL_PAD_LCD_DATA22__LCDIF_DATA22  0x79
 444                         MX6UL_PAD_LCD_DATA23__LCDIF_DATA23  0x79
 445                 >;
 446         };
 447
 448         pinctrl_lcdif_ctrl: lcdifctrlgrp {
 449                 fsl,pins = <
 450                         MX6UL_PAD_LCD_CLK__LCDIF_CLK        0x79
 451                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
 452                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
 453                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
 454                         /* used for lcd reset */
 455                         MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09  0x79
 456                 >;
 457         };
 458
 459         pinctrl_qspi: qspigrp {
 460                 fsl,pins = <
 461                         MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK        0x70a1
 462                         MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00   0x70a1
 463                         MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01     0x70a1
 464                         MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02     0x70a1
 465                         MX6UL_PAD_NAND_CLE__QSPI_A_DATA03       0x70a1
 466                         MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B        0x70a1
 467                 >;
 468         };
 469
 470         pinctrl_sai2: sai2grp {
 471                 fsl,pins = <
 472                         MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK        0x17088
 473                         MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC        0x17088
 474                         MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA     0x11088
 475                         MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA        0x11088
 476                         MX6UL_PAD_JTAG_TMS__SAI2_MCLK           0x17088
 477                         MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04      0x17059
 478                 >;
 479         };
 480
 481         pinctrl_peri_3v3: peri3v3grp {
 482                 fsl,pins = <
 483                         MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02      0x1b0b0
 484                 >;
 485         };
 486
 487         pinctrl_pwm1: pwm1grp {
 488                 fsl,pins = <
 489                         MX6UL_PAD_GPIO1_IO08__PWM1_OUT   0x110b0
 490                 >;
 491         };
 492
 493         pinctrl_sim2: sim2grp {
 494                 fsl,pins = <
 495                         MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD             0xb808
 496                         MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK            0x31
 497                         MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B          0xb808
 498                         MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN           0xb808
 499                         MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD           0xb809
 500                         MX6UL_PAD_CSI_DATA02__GPIO4_IO23                0x3008
 501                 >;
 502         };
 503
 504         pinctrl_spi4: spi4grp {
 505                 fsl,pins = <
 506                         MX6UL_PAD_BOOT_MODE0__GPIO5_IO10        0x70a1
 507                         MX6UL_PAD_BOOT_MODE1__GPIO5_IO11        0x70a1
 508                         MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07      0x70a1
 509                         MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08      0x80000000
 510                 >;
 511         };
 512
 513         pinctrl_tsc: tscgrp {
 514                 fsl,pins = <
 515                         MX6UL_PAD_GPIO1_IO01__GPIO1_IO01                0xb0
 516                         MX6UL_PAD_GPIO1_IO02__GPIO1_IO02                0xb0
 517                         MX6UL_PAD_GPIO1_IO03__GPIO1_IO03                0xb0
 518                         MX6UL_PAD_GPIO1_IO04__GPIO1_IO04                0xb0
 519                 >;
 520         };
 521
 522         pinctrl_uart1: uart1grp {
 523                 fsl,pins = <
 524                         MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
 525                         MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
 526                 >;
 527         };
 528
 529         pinctrl_uart2: uart2grp {
 530                 fsl,pins = <
 531                         MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX   0x1b0b1
 532                         MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX   0x1b0b1
 533                         MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS  0x1b0b1
 534                         MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS  0x1b0b1
 535                 >;
 536         };
 537
 538         pinctrl_usb_otg1: usbotg1grp {
 539                 fsl,pins = <
 540                         MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID    0x17059
 541                 >;
 542         };
 543
 544         pinctrl_usdhc1: usdhc1grp {
 545                 fsl,pins = <
 546                         MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x17059
 547                         MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x10059
 548                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
 549                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
 550                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
 551                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
 552                         MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059 /* SD1 CD */
 553                         MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT    0x17059 /* SD1 VSELECT */
 554                         MX6UL_PAD_GPIO1_IO09__GPIO1_IO09        0x17059 /* SD1 RESET */
 555                 >;
 556         };
 557
 558         pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 559                 fsl,pins = <
 560                         MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
 561                         MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
 562                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
 563                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
 564                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
 565                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
 566
 567                 >;
 568         };
 569
 570         pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 571                 fsl,pins = <
 572                         MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
 573                         MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
 574                         MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
 575                         MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
 576                         MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
 577                         MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
 578                 >;
 579         };
 580
 581         pinctrl_usdhc2: usdhc2grp {
 582                 fsl,pins = <
 583                         MX6UL_PAD_NAND_RE_B__USDHC2_CLK     0x17059
 584                         MX6UL_PAD_NAND_WE_B__USDHC2_CMD     0x17059
 585                         MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
 586                         MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
 587                         MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
 588                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
 589                 >;
 590         };
 591
 592         pinctrl_wdog: wdoggrp {
 593                 fsl,pins = <
 594                         MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
 595                 >;
 596         };
 597 };