| blob | 251007a7b8366c09f8f60a99a1ea8fef9addd588 |
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 //
3 // Copyright 2015 Freescale Semiconductor, Inc.
4 // Copyright 2016 Toradex AG
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
14 / {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 /*
18 * The decompressor and also some bootloaders rely on a
19 * pre-existing /chosen node to be available to insert the
20 * command line and merge other ATAGS info.
21 */
22 chosen {};
24 aliases {
25 gpio0 = &gpio1;
26 gpio1 = &gpio2;
27 gpio2 = &gpio3;
28 gpio3 = &gpio4;
29 gpio4 = &gpio5;
30 gpio5 = &gpio6;
31 gpio6 = &gpio7;
32 i2c0 = &i2c1;
33 i2c1 = &i2c2;
34 i2c2 = &i2c3;
35 i2c3 = &i2c4;
36 mmc0 = &usdhc1;
37 mmc1 = &usdhc2;
38 mmc2 = &usdhc3;
39 serial0 = &uart1;
40 serial1 = &uart2;
41 serial2 = &uart3;
42 serial3 = &uart4;
43 serial4 = &uart5;
44 serial5 = &uart6;
45 serial6 = &uart7;
46 spi0 = &ecspi1;
47 spi1 = &ecspi2;
48 spi2 = &ecspi3;
49 spi3 = &ecspi4;
50 usb0 = &usbotg1;
51 usb1 = &usbh;
52 };
54 cpus {
55 #address-cells = <1>;
56 #size-cells = <0>;
58 idle-states {
59 entry-method = "psci";
61 cpu_sleep_wait: cpu-sleep-wait {
62 compatible = "arm,idle-state";
63 arm,psci-suspend-param = <0x0010000>;
64 local-timer-stop;
65 entry-latency-us = <100>;
66 exit-latency-us = <50>;
67 min-residency-us = <1000>;
68 };
69 };
71 cpu0: cpu@0 {
72 compatible = "arm,cortex-a7";
73 device_type = "cpu";
74 reg = <0>;
75 clock-frequency = <792000000>;
76 clock-latency = <61036>; /* two CLK32 periods */
77 clocks = <&clks IMX7D_CLK_ARM>;
78 cpu-idle-states = <&cpu_sleep_wait>;
79 };
80 };
82 ckil: clock-cki {
83 compatible = "fixed-clock";
84 #clock-cells = <0>;
85 clock-frequency = <32768>;
86 clock-output-names = "ckil";
87 };
89 osc: clock-osc {
90 compatible = "fixed-clock";
91 #clock-cells = <0>;
92 clock-frequency = <24000000>;
93 clock-output-names = "osc";
94 };
96 usbphynop1: usbphynop1 {
97 compatible = "usb-nop-xceiv";
98 clocks = <&clks IMX7D_USB_PHY1_CLK>;
99 clock-names = "main_clk";
100 #phy-cells = <0>;
101 };
103 usbphynop3: usbphynop3 {
104 compatible = "usb-nop-xceiv";
105 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
106 clock-names = "main_clk";
107 #phy-cells = <0>;
108 };
110 pmu {
111 compatible = "arm,cortex-a7-pmu";
112 interrupt-parent = <&gpc>;
113 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
114 interrupt-affinity = <&cpu0>;
115 };
117 replicator {
118 /*
119 * non-configurable replicators don't show up on the
120 * AMBA bus. As such no need to add "arm,primecell"
121 */
122 compatible = "arm,coresight-static-replicator";
124 out-ports {
125 #address-cells = <1>;
126 #size-cells = <0>;
127 /* replicator output ports */
128 port@0 {
129 reg = <0>;
130 replicator_out_port0: endpoint {
131 remote-endpoint = <&tpiu_in_port>;
132 };
133 };
135 port@1 {
136 reg = <1>;
137 replicator_out_port1: endpoint {
138 remote-endpoint = <&etr_in_port>;
139 };
140 };
141 };
143 in-ports {
144 port {
145 replicator_in_port0: endpoint {
146 remote-endpoint = <&etf_out_port>;
147 };
148 };
149 };
150 };
152 timer {
153 compatible = "arm,armv7-timer";
154 interrupt-parent = <&intc>;
155 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
156 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
157 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
158 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
159 };
161 soc {
162 #address-cells = <1>;
163 #size-cells = <1>;
164 compatible = "simple-bus";
165 interrupt-parent = <&gpc>;
166 ranges;
168 funnel@30041000 {
169 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
170 reg = <0x30041000 0x1000>;
171 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
172 clock-names = "apb_pclk";
174 ca_funnel_in_ports: in-ports {
175 port {
176 ca_funnel_in_port0: endpoint {
177 remote-endpoint = <&etm0_out_port>;
178 };
179 };
181 /* the other input ports are not connect to anything */
182 };
184 out-ports {
185 port {
186 ca_funnel_out_port0: endpoint {
187 remote-endpoint = <&hugo_funnel_in_port0>;
188 };
189 };
191 };
192 };
194 etm@3007c000 {
195 compatible = "arm,coresight-etm3x", "arm,primecell";
196 reg = <0x3007c000 0x1000>;
197 cpu = <&cpu0>;
198 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
199 clock-names = "apb_pclk";
201 out-ports {
202 port {
203 etm0_out_port: endpoint {
204 remote-endpoint = <&ca_funnel_in_port0>;
205 };
206 };
207 };
208 };
210 funnel@30083000 {
211 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
212 reg = <0x30083000 0x1000>;
213 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
214 clock-names = "apb_pclk";
216 in-ports {
217 #address-cells = <1>;
218 #size-cells = <0>;
220 port@0 {
221 reg = <0>;
222 hugo_funnel_in_port0: endpoint {
223 remote-endpoint = <&ca_funnel_out_port0>;
224 };
225 };
227 port@1 {
228 reg = <1>;
229 hugo_funnel_in_port1: endpoint {
230 /* M4 input */
231 };
232 };
233 /* the other input ports are not connect to anything */
234 };
236 out-ports {
237 port {
238 hugo_funnel_out_port0: endpoint {
239 remote-endpoint = <&etf_in_port>;
240 };
241 };
242 };
243 };
245 etf@30084000 {
246 compatible = "arm,coresight-tmc", "arm,primecell";
247 reg = <0x30084000 0x1000>;
248 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
249 clock-names = "apb_pclk";
251 in-ports {
252 port {
253 etf_in_port: endpoint {
254 remote-endpoint = <&hugo_funnel_out_port0>;
255 };
256 };
257 };
259 out-ports {
260 port {
261 etf_out_port: endpoint {
262 remote-endpoint = <&replicator_in_port0>;
263 };
264 };
265 };
266 };
268 etr@30086000 {
269 compatible = "arm,coresight-tmc", "arm,primecell";
270 reg = <0x30086000 0x1000>;
271 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
272 clock-names = "apb_pclk";
274 in-ports {
275 port {
276 etr_in_port: endpoint {
277 remote-endpoint = <&replicator_out_port1>;
278 };
279 };
280 };
281 };
283 tpiu@30087000 {
284 compatible = "arm,coresight-tpiu", "arm,primecell";
285 reg = <0x30087000 0x1000>;
286 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
287 clock-names = "apb_pclk";
289 in-ports {
290 port {
291 tpiu_in_port: endpoint {
292 remote-endpoint = <&replicator_out_port0>;
293 };
294 };
295 };
296 };
298 intc: interrupt-controller@31001000 {
299 compatible = "arm,cortex-a7-gic";
300 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
301 #interrupt-cells = <3>;
302 interrupt-controller;
303 interrupt-parent = <&intc>;
304 reg = <0x31001000 0x1000>,
305 <0x31002000 0x2000>,
306 <0x31004000 0x2000>,
307 <0x31006000 0x2000>;
308 };
310 aips1: bus@30000000 {
311 compatible = "fsl,aips-bus", "simple-bus";
312 #address-cells = <1>;
313 #size-cells = <1>;
314 reg = <0x30000000 0x400000>;
315 ranges;
317 gpio1: gpio@30200000 {
318 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
319 reg = <0x30200000 0x10000>;
320 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
321 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
322 gpio-controller;
323 #gpio-cells = <2>;
324 interrupt-controller;
325 #interrupt-cells = <2>;
326 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
327 };
329 gpio2: gpio@30210000 {
330 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
331 reg = <0x30210000 0x10000>;
332 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
334 gpio-controller;
335 #gpio-cells = <2>;
336 interrupt-controller;
337 #interrupt-cells = <2>;
338 gpio-ranges = <&iomuxc 0 13 32>;
339 };
341 gpio3: gpio@30220000 {
342 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
343 reg = <0x30220000 0x10000>;
344 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
346 gpio-controller;
347 #gpio-cells = <2>;
348 interrupt-controller;
349 #interrupt-cells = <2>;
350 gpio-ranges = <&iomuxc 0 45 29>;
351 };
353 gpio4: gpio@30230000 {
354 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
355 reg = <0x30230000 0x10000>;
356 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
358 gpio-controller;
359 #gpio-cells = <2>;
360 interrupt-controller;
361 #interrupt-cells = <2>;
362 gpio-ranges = <&iomuxc 0 74 24>;
363 };
365 gpio5: gpio@30240000 {
366 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
367 reg = <0x30240000 0x10000>;
368 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
369 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
370 gpio-controller;
371 #gpio-cells = <2>;
372 interrupt-controller;
373 #interrupt-cells = <2>;
374 gpio-ranges = <&iomuxc 0 98 18>;
375 };
377 gpio6: gpio@30250000 {
378 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
379 reg = <0x30250000 0x10000>;
380 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
381 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
382 gpio-controller;
383 #gpio-cells = <2>;
384 interrupt-controller;
385 #interrupt-cells = <2>;
386 gpio-ranges = <&iomuxc 0 116 23>;
387 };
389 gpio7: gpio@30260000 {
390 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
391 reg = <0x30260000 0x10000>;
392 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
393 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
394 gpio-controller;
395 #gpio-cells = <2>;
396 interrupt-controller;
397 #interrupt-cells = <2>;
398 gpio-ranges = <&iomuxc 0 139 16>;
399 };
401 wdog1: watchdog@30280000 {
402 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
403 reg = <0x30280000 0x10000>;
404 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
406 };
408 wdog2: watchdog@30290000 {
409 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
410 reg = <0x30290000 0x10000>;
411 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
412 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
413 status = "disabled";
414 };
416 wdog3: watchdog@302a0000 {
417 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
418 reg = <0x302a0000 0x10000>;
419 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
421 status = "disabled";
422 };
424 wdog4: watchdog@302b0000 {
425 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
426 reg = <0x302b0000 0x10000>;
427 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
429 status = "disabled";
430 };
432 iomuxc_lpsr: iomuxc-lpsr@302c0000 {
433 compatible = "fsl,imx7d-iomuxc-lpsr";
434 reg = <0x302c0000 0x10000>;
435 fsl,input-sel = <&iomuxc>;
436 };
438 gpt1: timer@302d0000 {
439 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
440 reg = <0x302d0000 0x10000>;
441 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&clks IMX7D_GPT1_ROOT_CLK>,
443 <&clks IMX7D_GPT1_ROOT_CLK>;
444 clock-names = "ipg", "per";
445 };
447 gpt2: timer@302e0000 {
448 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
449 reg = <0x302e0000 0x10000>;
450 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&clks IMX7D_GPT2_ROOT_CLK>,
452 <&clks IMX7D_GPT2_ROOT_CLK>;
453 clock-names = "ipg", "per";
454 status = "disabled";
455 };
457 gpt3: timer@302f0000 {
458 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
459 reg = <0x302f0000 0x10000>;
460 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&clks IMX7D_GPT3_ROOT_CLK>,
462 <&clks IMX7D_GPT3_ROOT_CLK>;
463 clock-names = "ipg", "per";
464 status = "disabled";
465 };
467 gpt4: timer@30300000 {
468 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
469 reg = <0x30300000 0x10000>;
470 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&clks IMX7D_GPT4_ROOT_CLK>,
472 <&clks IMX7D_GPT4_ROOT_CLK>;
473 clock-names = "ipg", "per";
474 status = "disabled";
475 };
477 kpp: keypad@30320000 {
478 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
479 reg = <0x30320000 0x10000>;
480 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&clks IMX7D_KPP_ROOT_CLK>;
482 status = "disabled";
483 };
485 iomuxc: pinctrl@30330000 {
486 compatible = "fsl,imx7d-iomuxc";
487 reg = <0x30330000 0x10000>;
488 };
490 gpr: iomuxc-gpr@30340000 {
491 compatible = "fsl,imx7d-iomuxc-gpr",
492 "fsl,imx6q-iomuxc-gpr", "syscon",
493 "simple-mfd";
494 reg = <0x30340000 0x10000>;
496 mux: mux-controller {
497 compatible = "mmio-mux";
498 #mux-control-cells = <0>;
499 mux-reg-masks = <0x14 0x00000010>;
500 };
502 video_mux: csi-mux {
503 compatible = "video-mux";
504 mux-controls = <&mux 0>;
505 #address-cells = <1>;
506 #size-cells = <0>;
507 status = "disabled";
509 port@0 {
510 reg = <0>;
511 };
513 port@1 {
514 reg = <1>;
516 csi_mux_from_mipi_vc0: endpoint {
517 remote-endpoint = <&mipi_vc0_to_csi_mux>;
518 };
519 };
521 port@2 {
522 reg = <2>;
524 csi_mux_to_csi: endpoint {
525 remote-endpoint = <&csi_from_csi_mux>;
526 };
527 };
528 };
529 };
531 ocotp: efuse@30350000 {
532 #address-cells = <1>;
533 #size-cells = <1>;
534 compatible = "fsl,imx7d-ocotp", "syscon";
535 reg = <0x30350000 0x10000>;
536 clocks = <&clks IMX7D_OCOTP_CLK>;
538 tempmon_calib: calib@3c {
539 reg = <0x3c 0x4>;
540 };
542 fuse_grade: fuse-grade@10 {
543 reg = <0x10 0x4>;
544 };
545 };
547 anatop: anatop@30360000 {
548 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
549 "syscon", "simple-mfd";
550 reg = <0x30360000 0x10000>;
551 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
554 reg_1p0d: regulator-vdd1p0d {
555 compatible = "fsl,anatop-regulator";
556 regulator-name = "vdd1p0d";
557 regulator-min-microvolt = <800000>;
558 regulator-max-microvolt = <1200000>;
559 anatop-reg-offset = <0x210>;
560 anatop-vol-bit-shift = <8>;
561 anatop-vol-bit-width = <5>;
562 anatop-min-bit-val = <8>;
563 anatop-min-voltage = <800000>;
564 anatop-max-voltage = <1200000>;
565 anatop-enable-bit = <0>;
566 };
568 reg_1p2: regulator-vdd1p2 {
569 compatible = "fsl,anatop-regulator";
570 regulator-name = "vdd1p2";
571 regulator-min-microvolt = <1100000>;
572 regulator-max-microvolt = <1300000>;
573 anatop-reg-offset = <0x220>;
574 anatop-vol-bit-shift = <8>;
575 anatop-vol-bit-width = <5>;
576 anatop-min-bit-val = <0x14>;
577 anatop-min-voltage = <1100000>;
578 anatop-max-voltage = <1300000>;
579 anatop-enable-bit = <0>;
580 };
582 tempmon: tempmon {
583 compatible = "fsl,imx7d-tempmon";
584 interrupt-parent = <&gpc>;
585 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
586 fsl,tempmon = <&anatop>;
587 nvmem-cells = <&tempmon_calib>, <&fuse_grade>;
588 nvmem-cell-names = "calib", "temp_grade";
589 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
590 };
591 };
593 snvs: snvs@30370000 {
594 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
595 reg = <0x30370000 0x10000>;
597 snvs_rtc: snvs-rtc-lp {
598 compatible = "fsl,sec-v4.0-mon-rtc-lp";
599 regmap = <&snvs>;
600 offset = <0x34>;
601 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
602 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&clks IMX7D_SNVS_CLK>;
604 clock-names = "snvs-rtc";
605 };
607 snvs_pwrkey: snvs-powerkey {
608 compatible = "fsl,sec-v4.0-pwrkey";
609 regmap = <&snvs>;
610 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
611 clocks = <&clks IMX7D_SNVS_CLK>;
612 clock-names = "snvs-pwrkey";
613 linux,keycode = <KEY_POWER>;
614 wakeup-source;
615 status = "disabled";
616 };
617 };
619 clks: clock-controller@30380000 {
620 compatible = "fsl,imx7d-ccm";
621 reg = <0x30380000 0x10000>;
622 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
623 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
624 #clock-cells = <1>;
625 clocks = <&ckil>, <&osc>;
626 clock-names = "ckil", "osc";
627 };
629 src: reset-controller@30390000 {
630 compatible = "fsl,imx7d-src", "syscon";
631 reg = <0x30390000 0x10000>;
632 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
633 #reset-cells = <1>;
634 };
636 gpc: gpc@303a0000 {
637 compatible = "fsl,imx7d-gpc";
638 reg = <0x303a0000 0x10000>;
639 interrupt-controller;
640 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
641 #interrupt-cells = <3>;
642 interrupt-parent = <&intc>;
643 #power-domain-cells = <1>;
645 pgc {
646 #address-cells = <1>;
647 #size-cells = <0>;
649 pgc_mipi_phy: power-domain@0 {
650 #power-domain-cells = <0>;
651 reg = <0>;
652 power-supply = <®_1p0d>;
653 };
655 pgc_pcie_phy: power-domain@1 {
656 #power-domain-cells = <0>;
657 reg = <1>;
658 power-supply = <®_1p0d>;
659 };
661 pgc_hsic_phy: power-domain@2 {
662 #power-domain-cells = <0>;
663 reg = <2>;
664 power-supply = <®_1p2>;
665 };
666 };
667 };
668 };
670 aips2: bus@30400000 {
671 compatible = "fsl,aips-bus", "simple-bus";
672 #address-cells = <1>;
673 #size-cells = <1>;
674 reg = <0x30400000 0x400000>;
675 ranges;
677 adc1: adc@30610000 {
678 compatible = "fsl,imx7d-adc";
679 reg = <0x30610000 0x10000>;
680 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
682 clock-names = "adc";
683 #io-channel-cells = <1>;
684 status = "disabled";
685 };
687 adc2: adc@30620000 {
688 compatible = "fsl,imx7d-adc";
689 reg = <0x30620000 0x10000>;
690 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
692 clock-names = "adc";
693 #io-channel-cells = <1>;
694 status = "disabled";
695 };
697 ecspi4: spi@30630000 {
698 #address-cells = <1>;
699 #size-cells = <0>;
700 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
701 reg = <0x30630000 0x10000>;
702 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
704 <&clks IMX7D_ECSPI4_ROOT_CLK>;
705 clock-names = "ipg", "per";
706 status = "disabled";
707 };
709 pwm1: pwm@30660000 {
710 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
711 reg = <0x30660000 0x10000>;
712 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
714 <&clks IMX7D_PWM1_ROOT_CLK>;
715 clock-names = "ipg", "per";
716 #pwm-cells = <3>;
717 status = "disabled";
718 };
720 pwm2: pwm@30670000 {
721 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
722 reg = <0x30670000 0x10000>;
723 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
724 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
725 <&clks IMX7D_PWM2_ROOT_CLK>;
726 clock-names = "ipg", "per";
727 #pwm-cells = <3>;
728 status = "disabled";
729 };
731 pwm3: pwm@30680000 {
732 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
733 reg = <0x30680000 0x10000>;
734 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
735 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
736 <&clks IMX7D_PWM3_ROOT_CLK>;
737 clock-names = "ipg", "per";
738 #pwm-cells = <3>;
739 status = "disabled";
740 };
742 pwm4: pwm@30690000 {
743 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
744 reg = <0x30690000 0x10000>;
745 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
746 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
747 <&clks IMX7D_PWM4_ROOT_CLK>;
748 clock-names = "ipg", "per";
749 #pwm-cells = <3>;
750 status = "disabled";
751 };
753 csi: csi@30710000 {
754 compatible = "fsl,imx7-csi";
755 reg = <0x30710000 0x10000>;
756 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
757 clocks = <&clks IMX7D_CLK_DUMMY>,
758 <&clks IMX7D_CSI_MCLK_ROOT_CLK>,
759 <&clks IMX7D_CLK_DUMMY>;
760 clock-names = "axi", "mclk", "dcic";
761 status = "disabled";
763 port {
764 csi_from_csi_mux: endpoint {
765 remote-endpoint = <&csi_mux_to_csi>;
766 };
767 };
768 };
770 lcdif: lcdif@30730000 {
771 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
772 reg = <0x30730000 0x10000>;
773 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
775 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>;
776 clock-names = "pix", "axi";
777 status = "disabled";
778 };
780 mipi_csi: mipi-csi@30750000 {
781 compatible = "fsl,imx7-mipi-csi2";
782 reg = <0x30750000 0x10000>;
783 #address-cells = <1>;
784 #size-cells = <0>;
785 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
787 <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
788 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
789 clock-names = "pclk", "wrap", "phy";
790 power-domains = <&pgc_mipi_phy>;
791 phy-supply = <®_1p0d>;
792 resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
793 reset-names = "mrst";
794 status = "disabled";
796 port@0 {
797 reg = <0>;
798 };
800 port@1 {
801 reg = <1>;
803 mipi_vc0_to_csi_mux: endpoint {
804 remote-endpoint = <&csi_mux_from_mipi_vc0>;
805 };
806 };
807 };
808 };
810 aips3: bus@30800000 {
811 compatible = "fsl,aips-bus", "simple-bus";
812 #address-cells = <1>;
813 #size-cells = <1>;
814 reg = <0x30800000 0x400000>;
815 ranges;
817 spba-bus@30800000 {
818 compatible = "fsl,spba-bus", "simple-bus";
819 #address-cells = <1>;
820 #size-cells = <1>;
821 reg = <0x30800000 0x100000>;
822 ranges;
824 ecspi1: spi@30820000 {
825 #address-cells = <1>;
826 #size-cells = <0>;
827 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
828 reg = <0x30820000 0x10000>;
829 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
830 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
831 <&clks IMX7D_ECSPI1_ROOT_CLK>;
832 clock-names = "ipg", "per";
833 status = "disabled";
834 };
836 ecspi2: spi@30830000 {
837 #address-cells = <1>;
838 #size-cells = <0>;
839 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
840 reg = <0x30830000 0x10000>;
841 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
842 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
843 <&clks IMX7D_ECSPI2_ROOT_CLK>;
844 clock-names = "ipg", "per";
845 status = "disabled";
846 };
848 ecspi3: spi@30840000 {
849 #address-cells = <1>;
850 #size-cells = <0>;
851 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
852 reg = <0x30840000 0x10000>;
853 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
854 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
855 <&clks IMX7D_ECSPI3_ROOT_CLK>;
856 clock-names = "ipg", "per";
857 status = "disabled";
858 };
860 uart1: serial@30860000 {
861 compatible = "fsl,imx7d-uart",
862 "fsl,imx6q-uart";
863 reg = <0x30860000 0x10000>;
864 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
866 <&clks IMX7D_UART1_ROOT_CLK>;
867 clock-names = "ipg", "per";
868 status = "disabled";
869 };
871 uart2: serial@30890000 {
872 compatible = "fsl,imx7d-uart",
873 "fsl,imx6q-uart";
874 reg = <0x30890000 0x10000>;
875 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
876 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
877 <&clks IMX7D_UART2_ROOT_CLK>;
878 clock-names = "ipg", "per";
879 status = "disabled";
880 };
882 uart3: serial@30880000 {
883 compatible = "fsl,imx7d-uart",
884 "fsl,imx6q-uart";
885 reg = <0x30880000 0x10000>;
886 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
887 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
888 <&clks IMX7D_UART3_ROOT_CLK>;
889 clock-names = "ipg", "per";
890 status = "disabled";
891 };
893 sai1: sai@308a0000 {
894 #sound-dai-cells = <0>;
895 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
896 reg = <0x308a0000 0x10000>;
897 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&clks IMX7D_SAI1_IPG_CLK>,
899 <&clks IMX7D_SAI1_ROOT_CLK>,
900 <&clks IMX7D_CLK_DUMMY>,
901 <&clks IMX7D_CLK_DUMMY>;
902 clock-names = "bus", "mclk1", "mclk2", "mclk3";
903 dma-names = "rx", "tx";
904 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
905 status = "disabled";
906 };
908 sai2: sai@308b0000 {
909 #sound-dai-cells = <0>;
910 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
911 reg = <0x308b0000 0x10000>;
912 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
913 clocks = <&clks IMX7D_SAI2_IPG_CLK>,
914 <&clks IMX7D_SAI2_ROOT_CLK>,
915 <&clks IMX7D_CLK_DUMMY>,
916 <&clks IMX7D_CLK_DUMMY>;
917 clock-names = "bus", "mclk1", "mclk2", "mclk3";
918 dma-names = "rx", "tx";
919 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
920 status = "disabled";
921 };
923 sai3: sai@308c0000 {
924 #sound-dai-cells = <0>;
925 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
926 reg = <0x308c0000 0x10000>;
927 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
928 clocks = <&clks IMX7D_SAI3_IPG_CLK>,
929 <&clks IMX7D_SAI3_ROOT_CLK>,
930 <&clks IMX7D_CLK_DUMMY>,
931 <&clks IMX7D_CLK_DUMMY>;
932 clock-names = "bus", "mclk1", "mclk2", "mclk3";
933 dma-names = "rx", "tx";
934 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
935 status = "disabled";
936 };
937 };
939 crypto: crypto@30900000 {
940 compatible = "fsl,sec-v4.0";
941 #address-cells = <1>;
942 #size-cells = <1>;
943 reg = <0x30900000 0x40000>;
944 ranges = <0 0x30900000 0x40000>;
945 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
946 clocks = <&clks IMX7D_CAAM_CLK>,
947 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
948 clock-names = "ipg", "aclk";
950 sec_jr0: jr@1000 {
951 compatible = "fsl,sec-v4.0-job-ring";
952 reg = <0x1000 0x1000>;
953 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
954 };
956 sec_jr1: jr@2000 {
957 compatible = "fsl,sec-v4.0-job-ring";
958 reg = <0x2000 0x1000>;
959 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
960 };
962 sec_jr2: jr@3000 {
963 compatible = "fsl,sec-v4.0-job-ring";
964 reg = <0x3000 0x1000>;
965 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
966 };
967 };
969 flexcan1: can@30a00000 {
970 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
971 reg = <0x30a00000 0x10000>;
972 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
973 clocks = <&clks IMX7D_CLK_DUMMY>,
974 <&clks IMX7D_CAN1_ROOT_CLK>;
975 clock-names = "ipg", "per";
976 fsl,stop-mode = <&gpr 0x10 1>;
977 status = "disabled";
978 };
980 flexcan2: can@30a10000 {
981 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
982 reg = <0x30a10000 0x10000>;
983 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
984 clocks = <&clks IMX7D_CLK_DUMMY>,
985 <&clks IMX7D_CAN2_ROOT_CLK>;
986 clock-names = "ipg", "per";
987 fsl,stop-mode = <&gpr 0x10 2>;
988 status = "disabled";
989 };
991 i2c1: i2c@30a20000 {
992 #address-cells = <1>;
993 #size-cells = <0>;
994 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
995 reg = <0x30a20000 0x10000>;
996 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
997 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
998 status = "disabled";
999 };
1001 i2c2: i2c@30a30000 {
1002 #address-cells = <1>;
1003 #size-cells = <0>;
1004 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1005 reg = <0x30a30000 0x10000>;
1006 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1007 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
1008 status = "disabled";
1009 };
1011 i2c3: i2c@30a40000 {
1012 #address-cells = <1>;
1013 #size-cells = <0>;
1014 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1015 reg = <0x30a40000 0x10000>;
1016 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1017 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
1018 status = "disabled";
1019 };
1021 i2c4: i2c@30a50000 {
1022 #address-cells = <1>;
1023 #size-cells = <0>;
1024 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
1025 reg = <0x30a50000 0x10000>;
1026 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1027 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
1028 status = "disabled";
1029 };
1031 uart4: serial@30a60000 {
1032 compatible = "fsl,imx7d-uart",
1033 "fsl,imx6q-uart";
1034 reg = <0x30a60000 0x10000>;
1035 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1036 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
1037 <&clks IMX7D_UART4_ROOT_CLK>;
1038 clock-names = "ipg", "per";
1039 status = "disabled";
1040 };
1042 uart5: serial@30a70000 {
1043 compatible = "fsl,imx7d-uart",
1044 "fsl,imx6q-uart";
1045 reg = <0x30a70000 0x10000>;
1046 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1047 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
1048 <&clks IMX7D_UART5_ROOT_CLK>;
1049 clock-names = "ipg", "per";
1050 status = "disabled";
1051 };
1053 uart6: serial@30a80000 {
1054 compatible = "fsl,imx7d-uart",
1055 "fsl,imx6q-uart";
1056 reg = <0x30a80000 0x10000>;
1057 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1058 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
1059 <&clks IMX7D_UART6_ROOT_CLK>;
1060 clock-names = "ipg", "per";
1061 status = "disabled";
1062 };
1064 uart7: serial@30a90000 {
1065 compatible = "fsl,imx7d-uart",
1066 "fsl,imx6q-uart";
1067 reg = <0x30a90000 0x10000>;
1068 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1069 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
1070 <&clks IMX7D_UART7_ROOT_CLK>;
1071 clock-names = "ipg", "per";
1072 status = "disabled";
1073 };
1075 mu0a: mailbox@30aa0000 {
1076 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
1077 reg = <0x30aa0000 0x10000>;
1078 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1079 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1080 #mbox-cells = <2>;
1081 status = "disabled";
1082 };
1084 mu0b: mailbox@30ab0000 {
1085 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu";
1086 reg = <0x30ab0000 0x10000>;
1087 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1088 clocks = <&clks IMX7D_MU_ROOT_CLK>;
1089 #mbox-cells = <2>;
1090 fsl,mu-side-b;
1091 status = "disabled";
1092 };
1094 usbotg1: usb@30b10000 {
1095 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1096 reg = <0x30b10000 0x200>;
1097 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1098 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1099 fsl,usbphy = <&usbphynop1>;
1100 fsl,usbmisc = <&usbmisc1 0>;
1101 phy-clkgate-delay-us = <400>;
1102 status = "disabled";
1103 };
1105 usbh: usb@30b30000 {
1106 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
1107 reg = <0x30b30000 0x200>;
1108 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1109 power-domains = <&pgc_hsic_phy>;
1110 clocks = <&clks IMX7D_USB_CTRL_CLK>;
1111 fsl,usbphy = <&usbphynop3>;
1112 fsl,usbmisc = <&usbmisc3 0>;
1113 phy_type = "hsic";
1114 dr_mode = "host";
1115 phy-clkgate-delay-us = <400>;
1116 status = "disabled";
1117 };
1119 usbmisc1: usbmisc@30b10200 {
1120 #index-cells = <1>;
1121 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1122 reg = <0x30b10200 0x200>;
1123 };
1125 usbmisc3: usbmisc@30b30200 {
1126 #index-cells = <1>;
1127 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
1128 reg = <0x30b30200 0x200>;
1129 };
1131 usdhc1: mmc@30b40000 {
1132 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1133 reg = <0x30b40000 0x10000>;
1134 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1135 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1136 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1137 <&clks IMX7D_USDHC1_ROOT_CLK>;
1138 clock-names = "ipg", "ahb", "per";
1139 bus-width = <4>;
1140 status = "disabled";
1141 };
1143 usdhc2: mmc@30b50000 {
1144 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1145 reg = <0x30b50000 0x10000>;
1146 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1147 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1148 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1149 <&clks IMX7D_USDHC2_ROOT_CLK>;
1150 clock-names = "ipg", "ahb", "per";
1151 bus-width = <4>;
1152 status = "disabled";
1153 };
1155 usdhc3: mmc@30b60000 {
1156 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
1157 reg = <0x30b60000 0x10000>;
1158 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1159 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1160 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>,
1161 <&clks IMX7D_USDHC3_ROOT_CLK>;
1162 clock-names = "ipg", "ahb", "per";
1163 bus-width = <4>;
1164 status = "disabled";
1165 };
1167 qspi: spi@30bb0000 {
1168 compatible = "fsl,imx7d-qspi";
1169 reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>;
1170 reg-names = "QuadSPI", "QuadSPI-memory";
1171 #address-cells = <1>;
1172 #size-cells = <0>;
1173 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1174 clocks = <&clks IMX7D_QSPI_ROOT_CLK>,
1175 <&clks IMX7D_QSPI_ROOT_CLK>;
1176 clock-names = "qspi_en", "qspi";
1177 status = "disabled";
1178 };
1180 sdma: sdma@30bd0000 {
1181 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
1182 reg = <0x30bd0000 0x10000>;
1183 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1184 clocks = <&clks IMX7D_IPG_ROOT_CLK>,
1185 <&clks IMX7D_SDMA_CORE_CLK>;
1186 clock-names = "ipg", "ahb";
1187 #dma-cells = <3>;
1188 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1189 };
1191 fec1: ethernet@30be0000 {
1192 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
1193 reg = <0x30be0000 0x10000>;
1194 interrupt-names = "int0", "int1", "int2", "pps";
1195 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1196 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1197 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1198 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1199 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>,
1200 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
1201 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
1202 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
1203 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
1204 clock-names = "ipg", "ahb", "ptp",
1205 "enet_clk_ref", "enet_out";
1206 fsl,num-tx-queues = <3>;
1207 fsl,num-rx-queues = <3>;
1208 fsl,stop-mode = <&gpr 0x10 3>;
1209 status = "disabled";
1210 };
1211 };
1213 dma_apbh: dma-apbh@33000000 {
1214 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1215 reg = <0x33000000 0x2000>;
1216 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1217 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1218 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1219 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1220 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1221 #dma-cells = <1>;
1222 dma-channels = <4>;
1223 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1224 };
1226 gpmi: nand-controller@33002000{
1227 compatible = "fsl,imx7d-gpmi-nand";
1228 #address-cells = <1>;
1229 #size-cells = <1>;
1230 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1231 reg-names = "gpmi-nand", "bch";
1232 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1233 interrupt-names = "bch";
1234 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
1235 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
1236 clock-names = "gpmi_io", "gpmi_bch_apb";
1237 dmas = <&dma_apbh 0>;
1238 dma-names = "rx-tx";
1239 status = "disabled";
1240 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
1241 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;
1242 };
1243 };
1244 };