arch/arm/boot/dts/keystone-k2g-evm.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for K2G EVM
   4  *
   5  * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
   6  */
   7 /dts-v1/;
   8
   9 #include "keystone-k2g.dtsi"
  10
  11 / {
  12         compatible =  "ti,k2g-evm", "ti,k2g", "ti,keystone";
  13         model = "Texas Instruments K2G General Purpose EVM";
  14
  15         memory@800000000 {
  16                 device_type = "memory";
  17                 reg = <0x00000008 0x00000000 0x00000000 0x80000000>;
  18         };
  19
  20         reserved-memory {
  21                 #address-cells = <2>;
  22                 #size-cells = <2>;
  23                 ranges;
  24
  25                 dsp_common_memory: dsp-common-memory@81f800000 {
  26                         compatible = "shared-dma-pool";
  27                         reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
  28                         reusable;
  29                         status = "okay";
  30                 };
  31         };
  32
  33         vcc3v3_dcin_reg: fixedregulator-vcc3v3-dcin {
  34                 compatible = "regulator-fixed";
  35                 regulator-name = "mmc0_fixed";
  36                 regulator-min-microvolt = <3300000>;
  37                 regulator-max-microvolt = <3300000>;
  38                 regulator-always-on;
  39         };
  40
  41         vcc1v8_ldo1_reg: fixedregulator-vcc1v8-ldo1 {
  42                 compatible = "regulator-fixed";
  43                 regulator-name = "ldo1";
  44                 regulator-min-microvolt = <1800000>;
  45                 regulator-max-microvolt = <1800000>;
  46                 regulator-always-on;
  47         };
  48
  49         vcc1v8_ldo2_reg: fixedregulator-vcc1v8-ldo2 {
  50                 compatible = "regulator-fixed";
  51                 regulator-name = "ldo2";
  52                 regulator-min-microvolt = <1800000>;
  53                 regulator-max-microvolt = <1800000>;
  54                 regulator-always-on;
  55         };
  56
  57         hdmi: connector {
  58                 compatible = "hdmi-connector";
  59                 label = "hdmi";
  60
  61                 type = "a";
  62
  63                 port {
  64                         hdmi_connector_in: endpoint {
  65                                 remote-endpoint = <&sii9022_out>;
  66                         };
  67                 };
  68         };
  69
  70         aud_mclk: aud_mclk {
  71                 compatible = "fixed-clock";
  72                 #clock-cells = <0>;
  73                 clock-frequency = <12288000>;
  74         };
  75
  76         sound0: sound@0 {
  77                 compatible = "simple-audio-card";
  78                 simple-audio-card,name = "K2G-EVM";
  79                 simple-audio-card,widgets =
  80                         "Headphone", "Headphone Jack",
  81                         "Line", "Line In";
  82                 simple-audio-card,routing =
  83                         "Headphone Jack",       "HPLOUT",
  84                         "Headphone Jack",       "HPROUT",
  85                         "LINE1L",               "Line In",
  86                         "LINE1R",               "Line In";
  87
  88                 simple-audio-card,dai-link@0 {
  89                         format = "i2s";
  90                         bitclock-master = <&sound0_0_master>;
  91                         frame-master = <&sound0_0_master>;
  92                         sound0_0_master: cpu {
  93                                 sound-dai = <&mcasp2>;
  94                                 clocks = <&k2g_clks 0x6 1>;
  95                                 system-clock-direction-out;
  96                         };
  97
  98                         codec {
  99                                 sound-dai = <&tlv320aic3106>;
 100                                 clocks = <&aud_mclk>;
 101                         };
 102                 };
 103
 104                 simple-audio-card,dai-link@1 {
 105                         format = "i2s";
 106                         bitclock-master = <&sound0_1_master>;
 107                         frame-master = <&sound0_1_master>;
 108                         sound0_1_master: cpu {
 109                                 sound-dai = <&mcasp2>;
 110                                 clocks = <&k2g_clks 0x6 1>;
 111                                 system-clock-direction-out;
 112                         };
 113
 114                         codec {
 115                                 sound-dai = <&sii9022>;
 116                                 clocks = <&aud_mclk>;
 117                         };
 118                 };
 119         };
 120 };
 121
 122 &k2g_pinctrl {
 123         uart0_pins: pinmux_uart0_pins {
 124                 pinctrl-single,pins = <
 125                         K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* uart0_rxd.uart0_rxd */
 126                         K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0)      /* uart0_txd.uart0_txd */
 127                 >;
 128         };
 129
 130         mmc0_pins: pinmux_mmc0_pins {
 131                 pinctrl-single,pins = <
 132                         K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)        /* mmc0_dat3.mmc0_dat3 */
 133                         K2G_CORE_IOPAD(0x1304) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)        /* mmc0_dat2.mmc0_dat2 */
 134                         K2G_CORE_IOPAD(0x1308) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)        /* mmc0_dat1.mmc0_dat1 */
 135                         K2G_CORE_IOPAD(0x130c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)        /* mmc0_dat0.mmc0_dat0 */
 136                         K2G_CORE_IOPAD(0x1310) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)        /* mmc0_clk.mmc0_clk */
 137                         K2G_CORE_IOPAD(0x1314) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2)        /* mmc0_cmd.mmc0_cmd */
 138                         K2G_CORE_IOPAD(0x12ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3)        /* mmc0_sdcd.gpio1_12 */
 139                 >;
 140         };
 141
 142         mmc1_pins: pinmux_mmc1_pins {
 143                 pinctrl-single,pins = <
 144                         K2G_CORE_IOPAD(0x10ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat7.mmc1_dat7 */
 145                         K2G_CORE_IOPAD(0x10f0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat6.mmc1_dat6 */
 146                         K2G_CORE_IOPAD(0x10f4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat5.mmc1_dat5 */
 147                         K2G_CORE_IOPAD(0x10f8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat4.mmc1_dat4 */
 148                         K2G_CORE_IOPAD(0x10fc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat3.mmc1_dat3 */
 149                         K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat2.mmc1_dat2 */
 150                         K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat1.mmc1_dat1 */
 151                         K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_dat0.mmc1_dat0 */
 152                         K2G_CORE_IOPAD(0x110c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_clk.mmc1_clk */
 153                         K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* mmc1_cmd.mmc1_cmd */
 154                 >;
 155         };
 156
 157         i2c0_pins: pinmux_i2c0_pins {
 158                 pinctrl-single,pins = <
 159                         K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* i2c0_scl.i2c0_scl */
 160                         K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* i2c0_sda.i2c0_sda */
 161                 >;
 162         };
 163
 164         i2c1_pins: pinmux_i2c1_pins {
 165                 pinctrl-single,pins = <
 166                         K2G_CORE_IOPAD(0x1384) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* i2c1_scl.i2c1_scl */
 167                         K2G_CORE_IOPAD(0x1388) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0)        /* i2c1_sda.i2c1_sda */
 168                 >;
 169         };
 170
 171         ecap0_pins: ecap0_pins {
 172                 pinctrl-single,pins = <
 173                         K2G_CORE_IOPAD(0x1374) (BUFFER_CLASS_B | MUX_MODE4)     /* pr1_mdio_data.ecap0_in_apwm0_out */
 174                 >;
 175         };
 176
 177         spi1_pins: pinmux_spi1_pins {
 178                 pinctrl-single,pins = <
 179                         K2G_CORE_IOPAD(0x11a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* spi1_scs0.spi1_scs0 */
 180                         K2G_CORE_IOPAD(0x11ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* spi1_clk.spi1_clk */
 181                         K2G_CORE_IOPAD(0x11b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* spi1_miso.spi1_miso */
 182                         K2G_CORE_IOPAD(0x11b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* spi1_mosi.spi1_mosi */
 183                 >;
 184         };
 185
 186         qspi_pins: pinmux_qspi_pins {
 187                 pinctrl-single,pins = <
 188                         K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */
 189                         K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */
 190                         K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */
 191                         K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */
 192                         K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */
 193                         K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */
 194                         K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */
 195                 >;
 196         };
 197
 198         uart2_pins: pinmux_uart2_pins {
 199                 pinctrl-single,pins = <
 200                         K2G_CORE_IOPAD(0x11ec) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* uart2_rxd.uart2_rxd */
 201                         K2G_CORE_IOPAD(0x11f0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0)      /* uart2_txd.uart2_txd */
 202                 >;
 203         };
 204
 205         dcan0_pins: pinmux_dcan0_pins {
 206                 pinctrl-single,pins = <
 207                         K2G_CORE_IOPAD(0x11fc) (BUFFER_CLASS_B | PULL_DISABLE  | MUX_MODE0)     /* dcan0tx.dcan0tx */
 208                         K2G_CORE_IOPAD(0x1200) (BUFFER_CLASS_B | PIN_PULLDOWN  | MUX_MODE0)     /* dcan0rx.dcan0rx */
 209                 >;
 210         };
 211
 212         dcan1_pins: pinmux_dcan1_pins {
 213                 pinctrl-single,pins = <
 214                         K2G_CORE_IOPAD(0x1224) (BUFFER_CLASS_B | PULL_DISABLE  | MUX_MODE1)     /* qspicsn2.dcan1tx */
 215                         K2G_CORE_IOPAD(0x1228) (BUFFER_CLASS_B | PIN_PULLDOWN  | MUX_MODE1)     /* qspicsn3.dcan1rx */
 216                 >;
 217         };
 218
 219         emac_pins: pinmux_emac_pins {
 220                 pinctrl-single,pins = <
 221                         K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_RXD1.RGMII_RXD1 */
 222                         K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_RXD2.RGMII_RXD2 */
 223                         K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_RXD3.RGMII_RXD3 */
 224                         K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_RXD0.RGMII_RXD0 */
 225                         K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXD0.RGMII_TXD0 */
 226                         K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXD1.RGMII_TXD1 */
 227                         K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXD2.RGMII_TXD2 */
 228                         K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXD3.RGMII_TXD3 */
 229                         K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXCLK.RGMII_TXC */
 230                         K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_TXEN.RGMII_TXCTL */
 231                         K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_RXCLK.RGMII_RXC */
 232                         K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1)      /* MII_RXDV.RGMII_RXCTL */
 233                 >;
 234         };
 235
 236         mdio_pins: pinmux_mdio_pins {
 237                 pinctrl-single,pins = <
 238                         K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* MDIO_CLK.MDIO_CLK */
 239                         K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* MDIO_DATA.MDIO_DATA */
 240                 >;
 241         };
 242
 243         vout_pins: pinmux_vout_pins {
 244                 pinctrl-single,pins = <
 245                         K2G_CORE_IOPAD(0x1078) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata23.dssdata23 */
 246                         K2G_CORE_IOPAD(0x107c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata22.dssdata22 */
 247                         K2G_CORE_IOPAD(0x1080) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata21.dssdata21 */
 248                         K2G_CORE_IOPAD(0x1084) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata20.dssdata20 */
 249                         K2G_CORE_IOPAD(0x1088) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata19.dssdata19 */
 250                         K2G_CORE_IOPAD(0x108c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata18.dssdata18 */
 251                         K2G_CORE_IOPAD(0x1090) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata17.dssdata17 */
 252                         K2G_CORE_IOPAD(0x1094) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata16.dssdata16 */
 253                         K2G_CORE_IOPAD(0x1098) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata15.dssdata15 */
 254                         K2G_CORE_IOPAD(0x109c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata14.dssdata14 */
 255                         K2G_CORE_IOPAD(0x10a0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata13.dssdata13 */
 256                         K2G_CORE_IOPAD(0x10a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata12.dssdata12 */
 257                         K2G_CORE_IOPAD(0x10a8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata11.dssdata11 */
 258                         K2G_CORE_IOPAD(0x10ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata10.dssdata10 */
 259                         K2G_CORE_IOPAD(0x10b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata9.dssdata9 */
 260                         K2G_CORE_IOPAD(0x10b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata8.dssdata8 */
 261                         K2G_CORE_IOPAD(0x10b8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata7.dssdata7 */
 262                         K2G_CORE_IOPAD(0x10bc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata6.dssdata6 */
 263                         K2G_CORE_IOPAD(0x10c0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata5.dssdata5 */
 264                         K2G_CORE_IOPAD(0x10c4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata4.dssdata4 */
 265                         K2G_CORE_IOPAD(0x10c8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata3.dssdata3 */
 266                         K2G_CORE_IOPAD(0x10cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata2.dssdata2 */
 267                         K2G_CORE_IOPAD(0x10d0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata1.dssdata1 */
 268                         K2G_CORE_IOPAD(0x10d4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssdata0.dssdata0 */
 269                         K2G_CORE_IOPAD(0x10d8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssvsync.dssvsync */
 270                         K2G_CORE_IOPAD(0x10dc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsshsync.dsshsync */
 271                         K2G_CORE_IOPAD(0x10e0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dsspclk.dsspclk */
 272                         K2G_CORE_IOPAD(0x10e4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssde.dssde */
 273                         K2G_CORE_IOPAD(0x10e8) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dssfid.dssfid */
 274                 >;
 275         };
 276
 277         mcasp2_pins: pinmux_mcasp2_pins {
 278                 pinctrl-single,pins = <
 279                         K2G_CORE_IOPAD(0x1234) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo2.mcasp2_axr2 */
 280                         K2G_CORE_IOPAD(0x1238) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo3.mcasp2_axr3 */
 281                         K2G_CORE_IOPAD(0x1254) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo10.mcasp2_afsx */
 282                         K2G_CORE_IOPAD(0x125c) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE4) /* pr0_pru_gpo12.mcasp2_aclkx */
 283                 >;
 284         };
 285 };
 286
 287 &uart0 {
 288         pinctrl-names = "default";
 289         pinctrl-0 = <&uart0_pins>;
 290         status = "okay";
 291 };
 292
 293 &gpio1 {
 294         status = "okay";
 295 };
 296
 297 &mmc0 {
 298         pinctrl-names = "default";
 299         pinctrl-0 = <&mmc0_pins>;
 300         vmmc-supply = <&vcc3v3_dcin_reg>;
 301         vqmmc-supply = <&vcc3v3_dcin_reg>;
 302         cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
 303         status = "okay";
 304 };
 305
 306 &mmc1 {
 307         pinctrl-names = "default";
 308         pinctrl-0 = <&mmc1_pins>;
 309         vmmc-supply = <&vcc3v3_dcin_reg>; /* VCC3V3_EMMC is connected to VCC3V3_DCIN */
 310         vqmmc-supply = <&vcc1v8_ldo1_reg>;
 311         ti,non-removable;
 312         status = "okay";
 313 };
 314
 315 &dsp0 {
 316         memory-region = <&dsp_common_memory>;
 317         status = "okay";
 318 };
 319
 320 &i2c0 {
 321         pinctrl-names = "default";
 322         pinctrl-0 = <&i2c0_pins>;
 323         status = "okay";
 324
 325         eeprom@50 {
 326                 compatible = "atmel,24c1024";
 327                 reg = <0x50>;
 328         };
 329 };
 330
 331 &keystone_usb0 {
 332         status = "okay";
 333 };
 334
 335 &usb0_phy {
 336         status = "okay";
 337 };
 338
 339 &usb0 {
 340         dr_mode = "host";
 341         status = "okay";
 342 };
 343
 344 &keystone_usb1 {
 345         status = "okay";
 346 };
 347
 348 &usb1_phy {
 349         status = "okay";
 350 };
 351
 352 &usb1 {
 353         dr_mode = "peripheral";
 354         status = "okay";
 355 };
 356
 357 &ecap0 {
 358         status = "okay";
 359         pinctrl-names = "default";
 360         pinctrl-0 = <&ecap0_pins>;
 361 };
 362
 363 &spi1 {
 364         pinctrl-names = "default";
 365         pinctrl-0 = <&spi1_pins>;
 366         status = "okay";
 367
 368         spi_nor: flash@0 {
 369                 #address-cells = <1>;
 370                 #size-cells = <1>;
 371                 compatible = "jedec,spi-nor";
 372                 spi-max-frequency = <5000000>;
 373                 m25p,fast-read;
 374                 reg = <0>;
 375
 376                 partition@0 {
 377                         label = "u-boot-spl";
 378                         reg = <0x0 0x100000>;
 379                         read-only;
 380                 };
 381
 382                 partition@1 {
 383                         label = "misc";
 384                         reg = <0x100000 0xf00000>;
 385                 };
 386         };
 387 };
 388
 389 &qspi {
 390         status = "okay";
 391         pinctrl-names = "default";
 392         pinctrl-0 = <&qspi_pins>;
 393         cdns,rclk-en;
 394
 395         flash0: m25p80@0 {
 396                 compatible = "s25fl512s", "jedec,spi-nor";
 397                 reg = <0>;
 398                 spi-tx-bus-width = <1>;
 399                 spi-rx-bus-width = <4>;
 400                 spi-max-frequency = <96000000>;
 401                 #address-cells = <1>;
 402                 #size-cells = <1>;
 403                 cdns,read-delay = <5>;
 404                 cdns,tshsl-ns = <500>;
 405                 cdns,tsd2d-ns = <500>;
 406                 cdns,tchsh-ns = <119>;
 407                 cdns,tslch-ns = <119>;
 408
 409                 partition@0 {
 410                         label = "QSPI.u-boot-spl-os";
 411                         reg = <0x00000000 0x00100000>;
 412                 };
 413                 partition@1 {
 414                         label = "QSPI.u-boot-env";
 415                         reg = <0x00100000 0x00040000>;
 416                 };
 417                 partition@2 {
 418                         label = "QSPI.skern";
 419                         reg = <0x00140000 0x0040000>;
 420                 };
 421                 partition@3 {
 422                         label = "QSPI.pmmc-firmware";
 423                         reg = <0x00180000 0x0040000>;
 424                 };
 425                 partition@4 {
 426                         label = "QSPI.kernel";
 427                         reg = <0x001C0000 0x0800000>;
 428                 };
 429                 partition@5 {
 430                         label = "QSPI.file-system";
 431                         reg = <0x009C0000 0x3640000>;
 432                 };
 433         };
 434 };
 435
 436 &uart2 {
 437         pinctrl-names = "default";
 438         pinctrl-0 = <&uart2_pins>;
 439         status = "okay";
 440 };
 441
 442 &dcan0 {
 443         pinctrl-names = "default";
 444         pinctrl-0 = <&dcan0_pins>;
 445         status = "okay";
 446 };
 447
 448 &dcan1 {
 449         pinctrl-names = "default";
 450         pinctrl-0 = <&dcan1_pins>;
 451         status = "okay";
 452 };
 453
 454 &qmss {
 455         status = "okay";
 456 };
 457
 458 &knav_dmas {
 459         status = "okay";
 460 };
 461
 462 &mdio {
 463         pinctrl-names = "default";
 464         pinctrl-0 = <&mdio_pins>;
 465         status = "okay";
 466         ethphy0: ethernet-phy@0 {
 467                 reg = <0>;
 468         };
 469 };
 470
 471 &gbe0 {
 472         phy-handle = <&ethphy0>;
 473         phy-mode = "rgmii-rxid";
 474         status = "okay";
 475 };
 476
 477 &netcp {
 478         pinctrl-names = "default";
 479         pinctrl-0 = <&emac_pins>;
 480         status = "okay";
 481 };
 482
 483 &i2c1 {
 484         pinctrl-names = "default";
 485         pinctrl-0 = <&i2c1_pins>;
 486         status = "okay";
 487         clock-frequency = <400000>;
 488
 489         sii9022: sii9022@3b {
 490                 #sound-dai-cells = <0>;
 491                 compatible = "sil,sii9022";
 492                 reg = <0x3b>;
 493
 494                 sil,i2s-data-lanes = < 0 >;
 495                 clocks = <&aud_mclk>;
 496                 clock-names = "mclk";
 497
 498                 ports {
 499                         #address-cells = <1>;
 500                         #size-cells = <0>;
 501
 502                         port@0 {
 503                                 reg = <0>;
 504
 505                                 sii9022_in: endpoint {
 506                                         remote-endpoint = <&dpi_out>;
 507                                 };
 508                         };
 509
 510                         port@1 {
 511                                 reg = <1>;
 512
 513                                 sii9022_out: endpoint {
 514                                         remote-endpoint = <&hdmi_connector_in>;
 515                                 };
 516                         };
 517                 };
 518         };
 519
 520         tlv320aic3106: tlv320aic3106@1b {
 521                 #sound-dai-cells = <0>;
 522                 compatible = "ti,tlv320aic3106";
 523                 reg = <0x1b>;
 524                 status = "okay";
 525
 526                 /* Regulators */
 527                 AVDD-supply = <&vcc3v3_dcin_reg>;
 528                 IOVDD-supply = <&vcc3v3_dcin_reg>;
 529                 DRVDD-supply = <&vcc3v3_dcin_reg>;
 530                 DVDD-supply = <&vcc1v8_ldo2_reg>;
 531         };
 532 };
 533
 534 &dss {
 535         pinctrl-names = "default";
 536         pinctrl-0 = <&vout_pins>;
 537         status = "ok";
 538
 539         port {
 540                 dpi_out: endpoint {
 541                         remote-endpoint = <&sii9022_in>;
 542                         data-lines = <24>;
 543                 };
 544         };
 545 };
 546
 547 &k2g_clks {
 548         /* on the board 22.5792MHz is connected to AUDOSC_IN */
 549         assigned-clocks = <&k2g_clks 0x4c 2>;
 550         assigned-clock-rates = <22579200>;
 551 };
 552
 553 &mcasp2 {
 554         #sound-dai-cells = <0>;
 555
 556         pinctrl-names = "default";
 557         pinctrl-0 = <&mcasp2_pins>;
 558
 559         assigned-clocks = <&k2g_clks 0x6 1>;
 560         assigned-clock-parents = <&k2g_clks 0x6 2>;
 561
 562         status = "okay";
 563
 564         op-mode = <0>;          /* MCASP_IIS_MODE */
 565         tdm-slots = <2>;
 566         /* 6 serializer */
 567         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 568                 0 0 1 2 0 0 // AXR2: TX, AXR3: rx
 569         >;
 570         tx-num-evt = <32>;
 571         rx-num-evt = <32>;
 572 };