arch/arm/boot/dts/meson8b.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright 2015 Endless Mobile, Inc.
   4  * Author: Carlo Caione <carlo@endlessm.com>
   5  */
   6
   7 #include <dt-bindings/clock/meson8-ddr-clkc.h>
   8 #include <dt-bindings/clock/meson8b-clkc.h>
   9 #include <dt-bindings/gpio/meson8b-gpio.h>
  10 #include <dt-bindings/power/meson8-power.h>
  11 #include <dt-bindings/reset/amlogic,meson8b-reset.h>
  12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
  13 #include "meson.dtsi"
  14
  15 / {
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu0: cpu@200 {
  21                         device_type = "cpu";
  22                         compatible = "arm,cortex-a5";
  23                         next-level-cache = <&L2>;
  24                         reg = <0x200>;
  25                         enable-method = "amlogic,meson8b-smp";
  26                         resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
  27                         operating-points-v2 = <&cpu_opp_table>;
  28                         clocks = <&clkc CLKID_CPUCLK>;
  29                 };
  30
  31                 cpu1: cpu@201 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a5";
  34                         next-level-cache = <&L2>;
  35                         reg = <0x201>;
  36                         enable-method = "amlogic,meson8b-smp";
  37                         resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
  38                         operating-points-v2 = <&cpu_opp_table>;
  39                         clocks = <&clkc CLKID_CPUCLK>;
  40                 };
  41
  42                 cpu2: cpu@202 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a5";
  45                         next-level-cache = <&L2>;
  46                         reg = <0x202>;
  47                         enable-method = "amlogic,meson8b-smp";
  48                         resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
  49                         operating-points-v2 = <&cpu_opp_table>;
  50                         clocks = <&clkc CLKID_CPUCLK>;
  51                 };
  52
  53                 cpu3: cpu@203 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a5";
  56                         next-level-cache = <&L2>;
  57                         reg = <0x203>;
  58                         enable-method = "amlogic,meson8b-smp";
  59                         resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
  60                         operating-points-v2 = <&cpu_opp_table>;
  61                         clocks = <&clkc CLKID_CPUCLK>;
  62                 };
  63         };
  64
  65         cpu_opp_table: opp-table {
  66                 compatible = "operating-points-v2";
  67                 opp-shared;
  68
  69                 opp-96000000 {
  70                         opp-hz = /bits/ 64 <96000000>;
  71                         opp-microvolt = <860000>;
  72                 };
  73                 opp-192000000 {
  74                         opp-hz = /bits/ 64 <192000000>;
  75                         opp-microvolt = <860000>;
  76                 };
  77                 opp-312000000 {
  78                         opp-hz = /bits/ 64 <312000000>;
  79                         opp-microvolt = <860000>;
  80                 };
  81                 opp-408000000 {
  82                         opp-hz = /bits/ 64 <408000000>;
  83                         opp-microvolt = <860000>;
  84                 };
  85                 opp-504000000 {
  86                         opp-hz = /bits/ 64 <504000000>;
  87                         opp-microvolt = <860000>;
  88                 };
  89                 opp-600000000 {
  90                         opp-hz = /bits/ 64 <600000000>;
  91                         opp-microvolt = <860000>;
  92                 };
  93                 opp-720000000 {
  94                         opp-hz = /bits/ 64 <720000000>;
  95                         opp-microvolt = <860000>;
  96                 };
  97                 opp-816000000 {
  98                         opp-hz = /bits/ 64 <816000000>;
  99                         opp-microvolt = <900000>;
 100                 };
 101                 opp-1008000000 {
 102                         opp-hz = /bits/ 64 <1008000000>;
 103                         opp-microvolt = <1140000>;
 104                 };
 105                 opp-1200000000 {
 106                         opp-hz = /bits/ 64 <1200000000>;
 107                         opp-microvolt = <1140000>;
 108                 };
 109                 opp-1320000000 {
 110                         opp-hz = /bits/ 64 <1320000000>;
 111                         opp-microvolt = <1140000>;
 112                 };
 113                 opp-1488000000 {
 114                         opp-hz = /bits/ 64 <1488000000>;
 115                         opp-microvolt = <1140000>;
 116                 };
 117                 opp-1536000000 {
 118                         opp-hz = /bits/ 64 <1536000000>;
 119                         opp-microvolt = <1140000>;
 120                 };
 121         };
 122
 123         gpu_opp_table: gpu-opp-table {
 124                 compatible = "operating-points-v2";
 125
 126                 opp-255000000 {
 127                         opp-hz = /bits/ 64 <255000000>;
 128                         opp-microvolt = <1100000>;
 129                 };
 130                 opp-364285714 {
 131                         opp-hz = /bits/ 64 <364285714>;
 132                         opp-microvolt = <1100000>;
 133                 };
 134                 opp-425000000 {
 135                         opp-hz = /bits/ 64 <425000000>;
 136                         opp-microvolt = <1100000>;
 137                 };
 138                 opp-510000000 {
 139                         opp-hz = /bits/ 64 <510000000>;
 140                         opp-microvolt = <1100000>;
 141                 };
 142                 opp-637500000 {
 143                         opp-hz = /bits/ 64 <637500000>;
 144                         opp-microvolt = <1100000>;
 145                         turbo-mode;
 146                 };
 147         };
 148
 149         pmu {
 150                 compatible = "arm,cortex-a5-pmu";
 151                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 152                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 153                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 154                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 155                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 156         };
 157
 158         reserved-memory {
 159                 #address-cells = <1>;
 160                 #size-cells = <1>;
 161                 ranges;
 162
 163                 /* 2 MiB reserved for Hardware ROM Firmware? */
 164                 hwrom@0 {
 165                         reg = <0x0 0x200000>;
 166                         no-map;
 167                 };
 168         };
 169
 170         mmcbus: bus@c8000000 {
 171                 compatible = "simple-bus";
 172                 reg = <0xc8000000 0x8000>;
 173                 #address-cells = <1>;
 174                 #size-cells = <1>;
 175                 ranges = <0x0 0xc8000000 0x8000>;
 176
 177                 ddr_clkc: clock-controller@400 {
 178                         compatible = "amlogic,meson8b-ddr-clkc";
 179                         reg = <0x400 0x20>;
 180                         clocks = <&xtal>;
 181                         clock-names = "xtal";
 182                         #clock-cells = <1>;
 183                 };
 184
 185                 dmcbus: bus@6000 {
 186                         compatible = "simple-bus";
 187                         reg = <0x6000 0x400>;
 188                         #address-cells = <1>;
 189                         #size-cells = <1>;
 190                         ranges = <0x0 0x6000 0x400>;
 191
 192                         canvas: video-lut@48 {
 193                                 compatible = "amlogic,meson8b-canvas",
 194                                              "amlogic,canvas";
 195                                 reg = <0x48 0x14>;
 196                         };
 197                 };
 198         };
 199
 200         apb: bus@d0000000 {
 201                 compatible = "simple-bus";
 202                 reg = <0xd0000000 0x200000>;
 203                 #address-cells = <1>;
 204                 #size-cells = <1>;
 205                 ranges = <0x0 0xd0000000 0x200000>;
 206
 207                 mali: gpu@c0000 {
 208                         compatible = "amlogic,meson8b-mali", "arm,mali-450";
 209                         reg = <0xc0000 0x40000>;
 210                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 211                                      <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 212                                      <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
 213                                      <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 214                                      <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
 215                                      <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
 216                                      <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
 217                                      <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 218                         interrupt-names = "gp", "gpmmu", "pp", "pmu",
 219                                           "pp0", "ppmmu0", "pp1", "ppmmu1";
 220                         resets = <&reset RESET_MALI>;
 221                         clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
 222                         clock-names = "bus", "core";
 223                         operating-points-v2 = <&gpu_opp_table>;
 224                 };
 225         };
 226 }; /* end of / */
 227
 228 &aobus {
 229         pmu: pmu@e0 {
 230                 compatible = "amlogic,meson8b-pmu", "syscon";
 231                 reg = <0xe0 0x18>;
 232         };
 233
 234         pinctrl_aobus: pinctrl@84 {
 235                 compatible = "amlogic,meson8b-aobus-pinctrl";
 236                 reg = <0x84 0xc>;
 237                 #address-cells = <1>;
 238                 #size-cells = <1>;
 239                 ranges;
 240
 241                 gpio_ao: ao-bank@14 {
 242                         reg = <0x14 0x4>,
 243                                 <0x2c 0x4>,
 244                                 <0x24 0x8>;
 245                         reg-names = "mux", "pull", "gpio";
 246                         gpio-controller;
 247                         #gpio-cells = <2>;
 248                         gpio-ranges = <&pinctrl_aobus 0 0 16>;
 249                 };
 250
 251                 uart_ao_a_pins: uart_ao_a {
 252                         mux {
 253                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
 254                                 function = "uart_ao";
 255                                 bias-disable;
 256                         };
 257                 };
 258
 259                 ir_recv_pins: remote {
 260                         mux {
 261                                 groups = "remote_input";
 262                                 function = "remote";
 263                                 bias-disable;
 264                         };
 265                 };
 266         };
 267 };
 268
 269 &cbus {
 270         reset: reset-controller@4404 {
 271                 compatible = "amlogic,meson8b-reset";
 272                 reg = <0x4404 0x9c>;
 273                 #reset-cells = <1>;
 274         };
 275
 276         analog_top: analog-top@81a8 {
 277                 compatible = "amlogic,meson8b-analog-top", "syscon";
 278                 reg = <0x81a8 0x14>;
 279         };
 280
 281         pwm_ef: pwm@86c0 {
 282                 compatible = "amlogic,meson8b-pwm";
 283                 reg = <0x86c0 0x10>;
 284                 #pwm-cells = <3>;
 285                 status = "disabled";
 286         };
 287
 288         clock-measure@8758 {
 289                 compatible = "amlogic,meson8b-clk-measure";
 290                 reg = <0x8758 0x1c>;
 291         };
 292
 293         pinctrl_cbus: pinctrl@9880 {
 294                 compatible = "amlogic,meson8b-cbus-pinctrl";
 295                 reg = <0x9880 0x10>;
 296                 #address-cells = <1>;
 297                 #size-cells = <1>;
 298                 ranges;
 299
 300                 gpio: banks@80b0 {
 301                         reg = <0x80b0 0x28>,
 302                                 <0x80e8 0x18>,
 303                                 <0x8120 0x18>,
 304                                 <0x8030 0x38>;
 305                         reg-names = "mux", "pull", "pull-enable", "gpio";
 306                         gpio-controller;
 307                         #gpio-cells = <2>;
 308                         gpio-ranges = <&pinctrl_cbus 0 0 83>;
 309                 };
 310
 311                 eth_rgmii_pins: eth-rgmii {
 312                         mux {
 313                                 groups = "eth_tx_clk",
 314                                          "eth_tx_en",
 315                                          "eth_txd1_0",
 316                                          "eth_txd0_0",
 317                                          "eth_rx_clk",
 318                                          "eth_rx_dv",
 319                                          "eth_rxd1",
 320                                          "eth_rxd0",
 321                                          "eth_mdio_en",
 322                                          "eth_mdc",
 323                                          "eth_ref_clk",
 324                                          "eth_txd2",
 325                                          "eth_txd3",
 326                                          "eth_rxd3",
 327                                          "eth_rxd2";
 328                                 function = "ethernet";
 329                                 bias-disable;
 330                         };
 331                 };
 332
 333                 eth_rmii_pins: eth-rmii {
 334                         mux {
 335                                 groups = "eth_tx_en",
 336                                          "eth_txd1_0",
 337                                          "eth_txd0_0",
 338                                          "eth_rx_clk",
 339                                          "eth_rx_dv",
 340                                          "eth_rxd1",
 341                                          "eth_rxd0",
 342                                          "eth_mdio_en",
 343                                          "eth_mdc";
 344                                 function = "ethernet";
 345                                 bias-disable;
 346                         };
 347                 };
 348
 349                 i2c_a_pins: i2c-a {
 350                         mux {
 351                                 groups = "i2c_sda_a", "i2c_sck_a";
 352                                 function = "i2c_a";
 353                                 bias-disable;
 354                         };
 355                 };
 356
 357                 sd_b_pins: sd-b {
 358                         mux {
 359                                 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
 360                                         "sd_d3_b", "sd_clk_b", "sd_cmd_b";
 361                                 function = "sd_b";
 362                                 bias-disable;
 363                         };
 364                 };
 365
 366                 sdxc_c_pins: sdxc-c {
 367                         mux {
 368                                 groups = "sdxc_d0_c", "sdxc_d13_c",
 369                                          "sdxc_d47_c", "sdxc_clk_c",
 370                                          "sdxc_cmd_c";
 371                                 function = "sdxc_c";
 372                                 bias-pull-up;
 373                         };
 374                 };
 375
 376                 pwm_c1_pins: pwm-c1 {
 377                         mux {
 378                                 groups = "pwm_c1";
 379                                 function = "pwm_c";
 380                                 bias-disable;
 381                         };
 382                 };
 383
 384                 pwm_d_pins: pwm-d {
 385                         mux {
 386                                 groups = "pwm_d";
 387                                 function = "pwm_d";
 388                                 bias-disable;
 389                         };
 390                 };
 391
 392                 uart_b0_pins: uart-b0 {
 393                         mux {
 394                                 groups = "uart_tx_b0",
 395                                        "uart_rx_b0";
 396                                 function = "uart_b";
 397                                 bias-disable;
 398                         };
 399                 };
 400
 401                 uart_b0_cts_rts_pins: uart-b0-cts-rts {
 402                         mux {
 403                                 groups = "uart_cts_b0",
 404                                        "uart_rts_b0";
 405                                 function = "uart_b";
 406                                 bias-disable;
 407                         };
 408                 };
 409         };
 410 };
 411
 412 &ahb_sram {
 413         smp-sram@1ff80 {
 414                 compatible = "amlogic,meson8b-smp-sram";
 415                 reg = <0x1ff80 0x8>;
 416         };
 417 };
 418
 419
 420 &efuse {
 421         compatible = "amlogic,meson8b-efuse";
 422         clocks = <&clkc CLKID_EFUSE>;
 423         clock-names = "core";
 424
 425         temperature_calib: calib@1f4 {
 426                 /* only the upper two bytes are relevant */
 427                 reg = <0x1f4 0x4>;
 428         };
 429 };
 430
 431 &ethmac {
 432         compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac";
 433
 434         reg = <0xc9410000 0x10000
 435                0xc1108140 0x4>;
 436
 437         clocks = <&clkc CLKID_ETH>,
 438                  <&clkc CLKID_MPLL2>,
 439                  <&clkc CLKID_MPLL2>,
 440                  <&clkc CLKID_FCLK_DIV2>;
 441         clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
 442         rx-fifo-depth = <4096>;
 443         tx-fifo-depth = <2048>;
 444
 445         resets = <&reset RESET_ETHERNET>;
 446         reset-names = "stmmaceth";
 447
 448         power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
 449 };
 450
 451 &gpio_intc {
 452         compatible = "amlogic,meson-gpio-intc",
 453                      "amlogic,meson8b-gpio-intc";
 454         status = "okay";
 455 };
 456
 457 &hhi {
 458         clkc: clock-controller {
 459                 compatible = "amlogic,meson8b-clkc";
 460                 clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
 461                 clock-names = "xtal", "ddr_pll";
 462                 #clock-cells = <1>;
 463                 #reset-cells = <1>;
 464         };
 465
 466         pwrc: power-controller {
 467                 compatible = "amlogic,meson8b-pwrc";
 468                 #power-domain-cells = <1>;
 469                 amlogic,ao-sysctrl = <&pmu>;
 470                 resets = <&reset RESET_DBLK>,
 471                          <&reset RESET_PIC_DC>,
 472                          <&reset RESET_HDMI_APB>,
 473                          <&reset RESET_HDMI_SYSTEM_RESET>,
 474                          <&reset RESET_VENCI>,
 475                          <&reset RESET_VENCP>,
 476                          <&reset RESET_VDAC_4>,
 477                          <&reset RESET_VENCL>,
 478                          <&reset RESET_VIU>,
 479                          <&reset RESET_VENC>,
 480                          <&reset RESET_RDMA>;
 481                 reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system",
 482                               "venci", "vencp", "vdac", "vencl", "viu",
 483                               "venc", "rdma";
 484                 clocks = <&clkc CLKID_VPU>;
 485                 clock-names = "vpu";
 486                 assigned-clocks = <&clkc CLKID_VPU>;
 487                 assigned-clock-rates = <182142857>;
 488         };
 489 };
 490
 491 &hwrng {
 492         compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
 493         clocks = <&clkc CLKID_RNG0>;
 494         clock-names = "core";
 495 };
 496
 497 &i2c_AO {
 498         clocks = <&clkc CLKID_CLK81>;
 499 };
 500
 501 &i2c_A {
 502         clocks = <&clkc CLKID_I2C>;
 503 };
 504
 505 &i2c_B {
 506         clocks = <&clkc CLKID_I2C>;
 507 };
 508
 509 &L2 {
 510         arm,data-latency = <3 3 3>;
 511         arm,tag-latency = <2 2 2>;
 512         arm,filter-ranges = <0x100000 0xc0000000>;
 513         prefetch-data = <1>;
 514         prefetch-instr = <1>;
 515         arm,shared-override;
 516 };
 517
 518 &periph {
 519         scu@0 {
 520                 compatible = "arm,cortex-a5-scu";
 521                 reg = <0x0 0x100>;
 522         };
 523
 524         timer@200 {
 525                 compatible = "arm,cortex-a5-global-timer";
 526                 reg = <0x200 0x20>;
 527                 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 528                 clocks = <&clkc CLKID_PERIPH>;
 529
 530                 /*
 531                  * the arm_global_timer driver currently does not handle clock
 532                  * rate changes. Keep it disabled for now.
 533                  */
 534                 status = "disabled";
 535         };
 536
 537         timer@600 {
 538                 compatible = "arm,cortex-a5-twd-timer";
 539                 reg = <0x600 0x20>;
 540                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 541                 clocks = <&clkc CLKID_PERIPH>;
 542         };
 543 };
 544
 545 &pwm_ab {
 546         compatible = "amlogic,meson8b-pwm";
 547 };
 548
 549 &pwm_cd {
 550         compatible = "amlogic,meson8b-pwm";
 551 };
 552
 553 &rtc {
 554         compatible = "amlogic,meson8b-rtc";
 555         resets = <&reset RESET_RTC>;
 556 };
 557
 558 &saradc {
 559         compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
 560         clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
 561         clock-names = "clkin", "core";
 562         amlogic,hhi-sysctrl = <&hhi>;
 563         nvmem-cells = <&temperature_calib>;
 564         nvmem-cell-names = "temperature_calib";
 565 };
 566
 567 &sdhc {
 568         compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
 569         clocks = <&xtal>,
 570                  <&clkc CLKID_FCLK_DIV4>,
 571                  <&clkc CLKID_FCLK_DIV3>,
 572                  <&clkc CLKID_FCLK_DIV5>,
 573                  <&clkc CLKID_SDHC>;
 574         clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
 575 };
 576
 577 &sdio {
 578         compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio";
 579         clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
 580         clock-names = "core", "clkin";
 581 };
 582
 583 &timer_abcde {
 584         clocks = <&xtal>, <&clkc CLKID_CLK81>;
 585         clock-names = "xtal", "pclk";
 586 };
 587
 588 &uart_AO {
 589         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
 590         clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_CLK81>;
 591         clock-names = "baud", "xtal", "pclk";
 592 };
 593
 594 &uart_A {
 595         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
 596         clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART0>;
 597         clock-names = "baud", "xtal", "pclk";
 598 };
 599
 600 &uart_B {
 601         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
 602         clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART1>;
 603         clock-names = "baud", "xtal", "pclk";
 604 };
 605
 606 &uart_C {
 607         compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
 608         clocks = <&clkc CLKID_CLK81>, <&xtal>, <&clkc CLKID_UART2>;
 609         clock-names = "baud", "xtal", "pclk";
 610 };
 611
 612 &usb0 {
 613         compatible = "amlogic,meson8b-usb", "snps,dwc2";
 614         clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
 615         clock-names = "otg";
 616 };
 617
 618 &usb1 {
 619         compatible = "amlogic,meson8b-usb", "snps,dwc2";
 620         clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
 621         clock-names = "otg";
 622 };
 623
 624 &usb0_phy {
 625         compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
 626         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
 627         clock-names = "usb_general", "usb";
 628         resets = <&reset RESET_USB_OTG>;
 629 };
 630
 631 &usb1_phy {
 632         compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
 633         clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
 634         clock-names = "usb_general", "usb";
 635         resets = <&reset RESET_USB_OTG>;
 636 };
 637
 638 &wdt {
 639         compatible = "amlogic,meson8b-wdt";
 640 };