| blob | 4ae630d37d094fd47505c1f26a142a70bbba28ca |
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 /*
3 * Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
4 */
6 #include <dt-bindings/clock/marvell,mmp2.h>
7 #include <dt-bindings/power/marvell,mmp2.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 / {
11 #address-cells = <1>;
12 #size-cells = <1>;
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17 enable-method = "marvell,mmp3-smp";
19 cpu@0 {
20 compatible = "marvell,pj4b";
21 device_type = "cpu";
22 next-level-cache = <&l2>;
23 reg = <0>;
24 };
26 cpu@1 {
27 compatible = "marvell,pj4b";
28 device_type = "cpu";
29 next-level-cache = <&l2>;
30 reg = <1>;
31 };
32 };
34 soc {
35 #address-cells = <1>;
36 #size-cells = <1>;
37 compatible = "simple-bus";
38 interrupt-parent = <&gic>;
39 ranges;
41 axi@d4200000 {
42 compatible = "simple-bus";
43 #address-cells = <1>;
44 #size-cells = <1>;
45 reg = <0xd4200000 0x00200000>;
46 ranges;
48 interrupt-controller@d4282000 {
49 compatible = "marvell,mmp3-intc";
50 interrupt-controller;
51 #interrupt-cells = <1>;
52 reg = <0xd4282000 0x1000>,
53 <0xd4284000 0x100>;
54 mrvl,intc-nr-irqs = <64>;
55 };
57 pmic_mux: interrupt-controller@d4282150 {
58 compatible = "mrvl,mmp2-mux-intc";
59 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
60 interrupt-controller;
61 #interrupt-cells = <1>;
62 reg = <0x150 0x4>, <0x168 0x4>;
63 reg-names = "mux status", "mux mask";
64 mrvl,intc-nr-irqs = <4>;
65 };
67 rtc_mux: interrupt-controller@d4282154 {
68 compatible = "mrvl,mmp2-mux-intc";
69 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
70 interrupt-controller;
71 #interrupt-cells = <1>;
72 reg = <0x154 0x4>, <0x16c 0x4>;
73 reg-names = "mux status", "mux mask";
74 mrvl,intc-nr-irqs = <2>;
75 };
77 hsi3_mux: interrupt-controller@d42821bc {
78 compatible = "mrvl,mmp2-mux-intc";
79 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
80 interrupt-controller;
81 #interrupt-cells = <1>;
82 reg = <0x1bc 0x4>, <0x1a4 0x4>;
83 reg-names = "mux status", "mux mask";
84 mrvl,intc-nr-irqs = <3>;
85 };
87 gpu_mux: interrupt-controller@d42821c0 {
88 compatible = "mrvl,mmp2-mux-intc";
89 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
90 interrupt-controller;
91 #interrupt-cells = <1>;
92 reg = <0x1c0 0x4>, <0x1a8 0x4>;
93 reg-names = "mux status", "mux mask";
94 mrvl,intc-nr-irqs = <3>;
95 };
97 twsi_mux: interrupt-controller@d4282158 {
98 compatible = "mrvl,mmp2-mux-intc";
99 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
100 interrupt-controller;
101 #interrupt-cells = <1>;
102 reg = <0x158 0x4>, <0x170 0x4>;
103 reg-names = "mux status", "mux mask";
104 mrvl,intc-nr-irqs = <5>;
105 };
107 hsi2_mux: interrupt-controller@d42821c4 {
108 compatible = "mrvl,mmp2-mux-intc";
109 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
110 interrupt-controller;
111 #interrupt-cells = <1>;
112 reg = <0x1c4 0x4>, <0x1ac 0x4>;
113 reg-names = "mux status", "mux mask";
114 mrvl,intc-nr-irqs = <2>;
115 };
117 dxo_mux: interrupt-controller@d42821c8 {
118 compatible = "mrvl,mmp2-mux-intc";
119 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
120 interrupt-controller;
121 #interrupt-cells = <1>;
122 reg = <0x1c8 0x4>, <0x1b0 0x4>;
123 reg-names = "mux status", "mux mask";
124 mrvl,intc-nr-irqs = <2>;
125 };
127 misc1_mux: interrupt-controller@d428215c {
128 compatible = "mrvl,mmp2-mux-intc";
129 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
130 interrupt-controller;
131 #interrupt-cells = <1>;
132 reg = <0x15c 0x4>, <0x174 0x4>;
133 reg-names = "mux status", "mux mask";
134 mrvl,intc-nr-irqs = <31>;
135 };
137 ci_mux: interrupt-controller@d42821cc {
138 compatible = "mrvl,mmp2-mux-intc";
139 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
140 interrupt-controller;
141 #interrupt-cells = <1>;
142 reg = <0x1cc 0x4>, <0x1b4 0x4>;
143 reg-names = "mux status", "mux mask";
144 mrvl,intc-nr-irqs = <2>;
145 };
147 ssp_mux: interrupt-controller@d4282160 {
148 compatible = "mrvl,mmp2-mux-intc";
149 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
150 interrupt-controller;
151 #interrupt-cells = <1>;
152 reg = <0x160 0x4>, <0x178 0x4>;
153 reg-names = "mux status", "mux mask";
154 mrvl,intc-nr-irqs = <2>;
155 };
157 hsi1_mux: interrupt-controller@d4282184 {
158 compatible = "mrvl,mmp2-mux-intc";
159 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
160 interrupt-controller;
161 #interrupt-cells = <1>;
162 reg = <0x184 0x4>, <0x17c 0x4>;
163 reg-names = "mux status", "mux mask";
164 mrvl,intc-nr-irqs = <4>;
165 };
167 misc2_mux: interrupt-controller@d4282188 {
168 compatible = "mrvl,mmp2-mux-intc";
169 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
170 interrupt-controller;
171 #interrupt-cells = <1>;
172 reg = <0x188 0x4>, <0x180 0x4>;
173 reg-names = "mux status", "mux mask";
174 mrvl,intc-nr-irqs = <20>;
175 };
177 hsi0_mux: interrupt-controller@d42821d0 {
178 compatible = "mrvl,mmp2-mux-intc";
179 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
180 interrupt-controller;
181 #interrupt-cells = <1>;
182 reg = <0x1d0 0x4>, <0x1b8 0x4>;
183 reg-names = "mux status", "mux mask";
184 mrvl,intc-nr-irqs = <5>;
185 };
187 usb_otg_phy0: usb-phy@d4207000 {
188 compatible = "marvell,mmp3-usb-phy";
189 reg = <0xd4207000 0x40>;
190 #phy-cells = <0>;
191 status = "disabled";
192 };
194 usb_otg0: usb@d4208000 {
195 compatible = "marvell,pxau2o-ehci";
196 reg = <0xd4208000 0x200>;
197 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
198 clocks = <&soc_clocks MMP2_CLK_USB>;
199 clock-names = "USBCLK";
200 phys = <&usb_otg_phy0>;
201 phy-names = "usb";
202 status = "disabled";
203 };
205 hsic_phy0: usb-phy@f0001800 {
206 compatible = "marvell,mmp3-hsic-phy";
207 reg = <0xf0001800 0x40>;
208 #phy-cells = <0>;
209 status = "disabled";
210 };
212 hsic0: usb@f0001000 {
213 compatible = "marvell,pxau2o-ehci";
214 reg = <0xf0001000 0x200>;
215 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&soc_clocks MMP2_CLK_USBHSIC0>;
217 clock-names = "USBCLK";
218 phys = <&hsic_phy0>;
219 phy-names = "usb";
220 phy_type = "hsic";
221 #address-cells = <0x01>;
222 #size-cells = <0x00>;
223 status = "disabled";
224 };
226 hsic_phy1: usb-phy@f0002800 {
227 compatible = "marvell,mmp3-hsic-phy";
228 reg = <0xf0002800 0x40>;
229 #phy-cells = <0>;
230 status = "disabled";
231 };
233 hsic1: usb@f0002000 {
234 compatible = "marvell,pxau2o-ehci";
235 reg = <0xf0002000 0x200>;
236 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&soc_clocks MMP2_CLK_USBHSIC1>;
238 clock-names = "USBCLK";
239 phys = <&hsic_phy1>;
240 phy-names = "usb";
241 phy_type = "hsic";
242 #address-cells = <0x01>;
243 #size-cells = <0x00>;
244 status = "disabled";
245 };
247 mmc1: mmc@d4280000 {
248 compatible = "mrvl,pxav3-mmc";
249 reg = <0xd4280000 0x120>;
250 clocks = <&soc_clocks MMP2_CLK_SDH0>;
251 clock-names = "io";
252 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
253 status = "disabled";
254 };
256 mmc2: mmc@d4280800 {
257 compatible = "mrvl,pxav3-mmc";
258 reg = <0xd4280800 0x120>;
259 clocks = <&soc_clocks MMP2_CLK_SDH1>;
260 clock-names = "io";
261 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
262 status = "disabled";
263 };
265 mmc3: mmc@d4281000 {
266 compatible = "mrvl,pxav3-mmc";
267 reg = <0xd4281000 0x120>;
268 clocks = <&soc_clocks MMP2_CLK_SDH2>;
269 clock-names = "io";
270 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
271 status = "disabled";
272 };
274 mmc4: mmc@d4281800 {
275 compatible = "mrvl,pxav3-mmc";
276 reg = <0xd4281800 0x120>;
277 clocks = <&soc_clocks MMP2_CLK_SDH3>;
278 clock-names = "io";
279 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
280 status = "disabled";
281 };
283 mmc5: mmc@d4217000 {
284 compatible = "mrvl,pxav3-mmc";
285 reg = <0xd4217000 0x120>;
286 clocks = <&soc_clocks MMP3_CLK_SDH4>;
287 clock-names = "io";
288 interrupt-parent = <&hsi1_mux>;
289 interrupts = <0>;
290 status = "disabled";
291 };
293 camera0: camera@d420a000 {
294 compatible = "marvell,mmp2-ccic";
295 reg = <0xd420a000 0x800>;
296 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&soc_clocks MMP2_CLK_CCIC0>;
298 clock-names = "axi";
299 power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>;
300 #clock-cells = <0>;
301 clock-output-names = "mclk";
302 status = "disabled";
303 };
305 camera1: camera@d420a800 {
306 compatible = "marvell,mmp2-ccic";
307 reg = <0xd420a800 0x800>;
308 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&soc_clocks MMP2_CLK_CCIC1>;
310 clock-names = "axi";
311 power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>;
312 #clock-cells = <0>;
313 clock-output-names = "mclk";
314 status = "disabled";
315 };
317 gpu_3d: gpu@d420d000 {
318 compatible = "vivante,gc";
319 reg = <0xd420d000 0x2000>;
320 interrupt-parent = <&gpu_mux>;
321 interrupts = <0>;
322 status = "disabled";
323 clocks = <&soc_clocks MMP3_CLK_GPU_3D>,
324 <&soc_clocks MMP3_CLK_GPU_BUS>;
325 clock-names = "core", "bus";
326 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
327 };
329 gpu_2d: gpu@d420f000 {
330 compatible = "vivante,gc";
331 reg = <0xd420f000 0x2000>;
332 interrupt-parent = <&gpu_mux>;
333 interrupts = <2>;
334 status = "disabled";
335 clocks = <&soc_clocks MMP3_CLK_GPU_2D>,
336 <&soc_clocks MMP3_CLK_GPU_BUS>;
337 clock-names = "core", "bus";
338 power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
339 };
340 };
342 apb@d4000000 {
343 compatible = "simple-bus";
344 #address-cells = <1>;
345 #size-cells = <1>;
346 reg = <0xd4000000 0x00200000>;
347 ranges;
349 timer: timer@d4014000 {
350 compatible = "mrvl,mmp-timer";
351 reg = <0xd4014000 0x100>;
352 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&soc_clocks MMP2_CLK_TIMER>;
354 };
356 uart1: serial@d4030000 {
357 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
358 reg = <0xd4030000 0x1000>;
359 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&soc_clocks MMP2_CLK_UART0>;
361 resets = <&soc_clocks MMP2_CLK_UART0>;
362 reg-shift = <2>;
363 status = "disabled";
364 };
366 uart2: serial@d4017000 {
367 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
368 reg = <0xd4017000 0x1000>;
369 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&soc_clocks MMP2_CLK_UART1>;
371 resets = <&soc_clocks MMP2_CLK_UART1>;
372 reg-shift = <2>;
373 status = "disabled";
374 };
376 uart3: serial@d4018000 {
377 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
378 reg = <0xd4018000 0x1000>;
379 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&soc_clocks MMP2_CLK_UART2>;
381 resets = <&soc_clocks MMP2_CLK_UART2>;
382 reg-shift = <2>;
383 status = "disabled";
384 };
386 uart4: serial@d4016000 {
387 compatible = "mrvl,mmp-uart", "intel,xscale-uart";
388 reg = <0xd4016000 0x1000>;
389 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&soc_clocks MMP2_CLK_UART3>;
391 resets = <&soc_clocks MMP2_CLK_UART3>;
392 reg-shift = <2>;
393 status = "disabled";
394 };
396 gpio: gpio@d4019000 {
397 compatible = "marvell,mmp2-gpio";
398 #address-cells = <1>;
399 #size-cells = <1>;
400 reg = <0xd4019000 0x1000>;
401 gpio-controller;
402 #gpio-cells = <2>;
403 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
404 interrupt-names = "gpio_mux";
405 clocks = <&soc_clocks MMP2_CLK_GPIO>;
406 resets = <&soc_clocks MMP2_CLK_GPIO>;
407 interrupt-controller;
408 #interrupt-cells = <2>;
409 ranges;
411 gcb0: gpio@d4019000 {
412 reg = <0xd4019000 0x4>;
413 };
415 gcb1: gpio@d4019004 {
416 reg = <0xd4019004 0x4>;
417 };
419 gcb2: gpio@d4019008 {
420 reg = <0xd4019008 0x4>;
421 };
423 gcb3: gpio@d4019100 {
424 reg = <0xd4019100 0x4>;
425 };
427 gcb4: gpio@d4019104 {
428 reg = <0xd4019104 0x4>;
429 };
431 gcb5: gpio@d4019108 {
432 reg = <0xd4019108 0x4>;
433 };
434 };
436 twsi1: i2c@d4011000 {
437 compatible = "mrvl,mmp-twsi";
438 reg = <0xd4011000 0x70>;
439 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&soc_clocks MMP2_CLK_TWSI0>;
441 resets = <&soc_clocks MMP2_CLK_TWSI0>;
442 #address-cells = <1>;
443 #size-cells = <0>;
444 mrvl,i2c-fast-mode;
445 status = "disabled";
446 };
448 twsi2: i2c@d4031000 {
449 compatible = "mrvl,mmp-twsi";
450 reg = <0xd4031000 0x70>;
451 interrupt-parent = <&twsi_mux>;
452 interrupts = <0>;
453 clocks = <&soc_clocks MMP2_CLK_TWSI1>;
454 resets = <&soc_clocks MMP2_CLK_TWSI1>;
455 #address-cells = <1>;
456 #size-cells = <0>;
457 status = "disabled";
458 };
460 twsi3: i2c@d4032000 {
461 compatible = "mrvl,mmp-twsi";
462 reg = <0xd4032000 0x70>;
463 interrupt-parent = <&twsi_mux>;
464 interrupts = <1>;
465 clocks = <&soc_clocks MMP2_CLK_TWSI2>;
466 resets = <&soc_clocks MMP2_CLK_TWSI2>;
467 #address-cells = <1>;
468 #size-cells = <0>;
469 status = "disabled";
470 };
472 twsi4: i2c@d4033000 {
473 compatible = "mrvl,mmp-twsi";
474 reg = <0xd4033000 0x70>;
475 interrupt-parent = <&twsi_mux>;
476 interrupts = <2>;
477 clocks = <&soc_clocks MMP2_CLK_TWSI3>;
478 resets = <&soc_clocks MMP2_CLK_TWSI3>;
479 #address-cells = <1>;
480 #size-cells = <0>;
481 status = "disabled";
482 };
485 twsi5: i2c@d4033800 {
486 compatible = "mrvl,mmp-twsi";
487 reg = <0xd4033800 0x70>;
488 interrupt-parent = <&twsi_mux>;
489 interrupts = <3>;
490 clocks = <&soc_clocks MMP2_CLK_TWSI4>;
491 resets = <&soc_clocks MMP2_CLK_TWSI4>;
492 #address-cells = <1>;
493 #size-cells = <0>;
494 status = "disabled";
495 };
497 twsi6: i2c@d4034000 {
498 compatible = "mrvl,mmp-twsi";
499 reg = <0xd4034000 0x70>;
500 interrupt-parent = <&twsi_mux>;
501 interrupts = <4>;
502 clocks = <&soc_clocks MMP2_CLK_TWSI5>;
503 resets = <&soc_clocks MMP2_CLK_TWSI5>;
504 #address-cells = <1>;
505 #size-cells = <0>;
506 status = "disabled";
507 };
509 rtc: rtc@d4010000 {
510 compatible = "mrvl,mmp-rtc";
511 reg = <0xd4010000 0x1000>;
512 interrupts = <1>, <0>;
513 interrupt-names = "rtc 1Hz", "rtc alarm";
514 interrupt-parent = <&rtc_mux>;
515 clocks = <&soc_clocks MMP2_CLK_RTC>;
516 resets = <&soc_clocks MMP2_CLK_RTC>;
517 status = "disabled";
518 };
520 ssp1: spi@d4035000 {
521 compatible = "marvell,mmp2-ssp";
522 reg = <0xd4035000 0x1000>;
523 clocks = <&soc_clocks MMP2_CLK_SSP0>;
524 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
525 #address-cells = <1>;
526 #size-cells = <0>;
527 status = "disabled";
528 };
530 ssp2: spi@d4036000 {
531 compatible = "marvell,mmp2-ssp";
532 reg = <0xd4036000 0x1000>;
533 clocks = <&soc_clocks MMP2_CLK_SSP1>;
534 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
535 #address-cells = <1>;
536 #size-cells = <0>;
537 status = "disabled";
538 };
540 ssp3: spi@d4037000 {
541 compatible = "marvell,mmp2-ssp";
542 reg = <0xd4037000 0x1000>;
543 clocks = <&soc_clocks MMP2_CLK_SSP2>;
544 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
545 #address-cells = <1>;
546 #size-cells = <0>;
547 status = "disabled";
548 };
550 ssp4: spi@d4039000 {
551 compatible = "marvell,mmp2-ssp";
552 reg = <0xd4039000 0x1000>;
553 clocks = <&soc_clocks MMP2_CLK_SSP3>;
554 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
555 #address-cells = <1>;
556 #size-cells = <0>;
557 status = "disabled";
558 };
559 };
561 l2: cache-controller@d0020000 {
562 compatible = "marvell,tauros3-cache", "arm,pl310-cache";
563 reg = <0xd0020000 0x1000>;
564 cache-unified;
565 cache-level = <2>;
566 };
568 soc_clocks: clocks@d4050000 {
569 compatible = "marvell,mmp3-clock";
570 reg = <0xd4050000 0x1000>,
571 <0xd4282800 0x400>,
572 <0xd4015000 0x1000>;
573 reg-names = "mpmu", "apmu", "apbc";
574 #clock-cells = <1>;
575 #reset-cells = <1>;
576 #power-domain-cells = <1>;
577 };
579 snoop-control-unit@e0000000 {
580 compatible = "arm,arm11mp-scu";
581 reg = <0xe0000000 0x100>;
582 };
584 gic: interrupt-controller@e0001000 {
585 compatible = "arm,arm11mp-gic";
586 interrupt-controller;
587 #interrupt-cells = <3>;
588 reg = <0xe0001000 0x1000>,
589 <0xe0000100 0x100>;
590 };
592 local-timer@e0000600 {
593 compatible = "arm,arm11mp-twd-timer";
594 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
595 IRQ_TYPE_EDGE_RISING)>;
596 reg = <0xe0000600 0x20>;
597 };
599 watchdog@e0000620 {
600 compatible = "arm,arm11mp-twd-wdt";
601 reg = <0xe0000620 0x20>;
602 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
603 IRQ_TYPE_EDGE_RISING)>;
604 };
605 };
606 };