arch/arm/boot/dts/nuvoton-npcm750-evb.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
   3 // Copyright 2018 Google, Inc.
   4
   5 /dts-v1/;
   6 #include "nuvoton-npcm750.dtsi"
   7 #include "dt-bindings/gpio/gpio.h"
   8 #include "nuvoton-npcm750-pincfg-evb.dtsi"
   9
  10 / {
  11         model = "Nuvoton npcm750 Development Board (Device Tree)";
  12         compatible = "nuvoton,npcm750";
  13
  14         aliases {
  15                 ethernet2 = &gmac0;
  16                 ethernet3 = &gmac1;
  17                 serial0 = &serial0;
  18                 serial1 = &serial1;
  19                 serial2 = &serial2;
  20                 serial3 = &serial3;
  21                 i2c0 = &i2c0;
  22                 i2c1 = &i2c1;
  23                 i2c2 = &i2c2;
  24                 i2c3 = &i2c3;
  25                 i2c4 = &i2c4;
  26                 i2c5 = &i2c5;
  27                 i2c6 = &i2c6;
  28                 i2c7 = &i2c7;
  29                 i2c8 = &i2c8;
  30                 i2c9 = &i2c9;
  31                 i2c10 = &i2c10;
  32                 i2c11 = &i2c11;
  33                 i2c12 = &i2c12;
  34                 i2c13 = &i2c13;
  35                 i2c14 = &i2c14;
  36                 i2c15 = &i2c15;
  37                 spi0 = &spi0;
  38                 spi1 = &spi1;
  39                 fiu0 = &fiu0;
  40                 fiu1 = &fiu3;
  41                 fiu2 = &fiux;
  42         };
  43
  44         chosen {
  45                 stdout-path = &serial3;
  46         };
  47
  48         memory {
  49                 device_type = "memory";
  50                 reg = <0x0 0x20000000>;
  51         };
  52 };
  53
  54 &gmac0 {
  55         phy-mode = "rgmii-id";
  56         status = "okay";
  57 };
  58
  59 &gmac1 {
  60         phy-mode = "rgmii-id";
  61         status = "okay";
  62 };
  63
  64 &ehci1 {
  65         status = "okay";
  66 };
  67
  68 &fiu0 {
  69         status = "okay";
  70         spi-nor@0 {
  71                 compatible = "jedec,spi-nor";
  72                 #address-cells = <1>;
  73                 #size-cells = <1>;
  74                 spi-rx-bus-width = <2>;
  75                 reg = <0>;
  76                 spi-max-frequency = <5000000>;
  77                 partitions@80000000 {
  78                         compatible = "fixed-partitions";
  79                         #address-cells = <1>;
  80                         #size-cells = <1>;
  81                         bbuboot1@0 {
  82                                 label = "bb-uboot-1";
  83                                 reg = <0x0000000 0x80000>;
  84                                 read-only;
  85                                 };
  86                         bbuboot2@80000 {
  87                                 label = "bb-uboot-2";
  88                                 reg = <0x0080000 0x80000>;
  89                                 read-only;
  90                                 };
  91                         envparam@100000 {
  92                                 label = "env-param";
  93                                 reg = <0x0100000 0x40000>;
  94                                 read-only;
  95                                 };
  96                         spare@140000 {
  97                                 label = "spare";
  98                                 reg = <0x0140000 0xC0000>;
  99                                 };
 100                         kernel@200000 {
 101                                 label = "kernel";
 102                                 reg = <0x0200000 0x400000>;
 103                                 };
 104                         rootfs@600000 {
 105                                 label = "rootfs";
 106                                 reg = <0x0600000 0x700000>;
 107                                 };
 108                         spare1@D00000 {
 109                                 label = "spare1";
 110                                 reg = <0x0D00000 0x200000>;
 111                                 };
 112                         spare2@0F00000 {
 113                                 label = "spare2";
 114                                 reg = <0x0F00000 0x200000>;
 115                                 };
 116                         spare3@1100000 {
 117                                 label = "spare3";
 118                                 reg = <0x1100000 0x200000>;
 119                                 };
 120                         spare4@1300000 {
 121                                 label = "spare4";
 122                                 reg = <0x1300000 0x0>;
 123                         };
 124                 };
 125         };
 126 };
 127
 128 &fiu3 {
 129         pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>;
 130         status = "okay";
 131         spi-nor@0 {
 132                 compatible = "jedec,spi-nor";
 133                 #address-cells = <1>;
 134                 #size-cells = <1>;
 135                 spi-rx-bus-width = <2>;
 136                 reg = <0>;
 137                 spi-max-frequency = <5000000>;
 138                 partitions@A0000000 {
 139                         compatible = "fixed-partitions";
 140                         #address-cells = <1>;
 141                         #size-cells = <1>;
 142                         system1@0 {
 143                                 label = "spi3-system1";
 144                                 reg = <0x0 0x0>;
 145                         };
 146                 };
 147         };
 148 };
 149
 150 &fiux {
 151         spix-mode;
 152 };
 153
 154 &watchdog1 {
 155         status = "okay";
 156 };
 157
 158 &rng {
 159         status = "okay";
 160 };
 161
 162 &serial0 {
 163         status = "okay";
 164 };
 165
 166 &serial1 {
 167         status = "okay";
 168 };
 169
 170 &serial2 {
 171         status = "okay";
 172 };
 173
 174 &serial3 {
 175         status = "okay";
 176 };
 177
 178 &adc {
 179         status = "okay";
 180 };
 181
 182 &lpc_kcs {
 183         kcs1: kcs1@0 {
 184                 status = "okay";
 185         };
 186
 187         kcs2: kcs2@0 {
 188                 status = "okay";
 189         };
 190
 191         kcs3: kcs3@0 {
 192                 status = "okay";
 193         };
 194 };
 195
 196 /* lm75 on SVB */
 197 &i2c0 {
 198         clock-frequency = <100000>;
 199         status = "okay";
 200         lm75@48 {
 201                 compatible = "lm75";
 202                 reg = <0x48>;
 203                 status = "okay";
 204         };
 205 };
 206
 207 /* lm75 on EB */
 208 &i2c1 {
 209         clock-frequency = <100000>;
 210         status = "okay";
 211         lm75@48 {
 212                 compatible = "lm75";
 213                 reg = <0x48>;
 214                 status = "okay";
 215         };
 216 };
 217
 218 /* tmp100 on EB */
 219 &i2c2 {
 220         clock-frequency = <100000>;
 221         status = "okay";
 222         tmp100@48 {
 223                 compatible = "tmp100";
 224                 reg = <0x48>;
 225                 status = "okay";
 226         };
 227 };
 228
 229 &i2c3 {
 230         clock-frequency = <100000>;
 231         status = "okay";
 232 };
 233
 234 &i2c5 {
 235         clock-frequency = <100000>;
 236         status = "okay";
 237 };
 238
 239 /* tmp100 on SVB */
 240 &i2c6 {
 241         clock-frequency = <100000>;
 242         status = "okay";
 243         tmp100@48 {
 244                 compatible = "tmp100";
 245                 reg = <0x48>;
 246                 status = "okay";
 247         };
 248 };
 249
 250 &i2c7 {
 251         clock-frequency = <100000>;
 252         status = "okay";
 253 };
 254
 255 &i2c8 {
 256         clock-frequency = <100000>;
 257         status = "okay";
 258 };
 259
 260 &i2c9 {
 261         clock-frequency = <100000>;
 262         status = "okay";
 263 };
 264
 265 &i2c10 {
 266         clock-frequency = <100000>;
 267         status = "okay";
 268 };
 269
 270 &i2c11 {
 271         clock-frequency = <100000>;
 272         status = "okay";
 273 };
 274
 275 &i2c14 {
 276         clock-frequency = <100000>;
 277         status = "okay";
 278 };
 279
 280 &pwm_fan {
 281         status = "okay";
 282         fan@0 {
 283                 reg = <0x00>;
 284                 fan-tach-ch = /bits/ 8 <0x00 0x01>;
 285                 cooling-levels = <127 255>;
 286         };
 287         fan@1 {
 288                 reg = <0x01>;
 289                 fan-tach-ch = /bits/ 8 <0x02 0x03>;
 290                 cooling-levels = /bits/ 8 <127 255>;
 291         };
 292         fan@2 {
 293                 reg = <0x02>;
 294                 fan-tach-ch = /bits/ 8 <0x04 0x05>;
 295                 cooling-levels = /bits/ 8 <127 255>;
 296         };
 297         fan@3 {
 298                 reg = <0x03>;
 299                 fan-tach-ch = /bits/ 8 <0x06 0x07>;
 300                 cooling-levels = /bits/ 8 <127 255>;
 301         };
 302         fan@4 {
 303                 reg = <0x04>;
 304                 fan-tach-ch = /bits/ 8 <0x08 0x09>;
 305                 cooling-levels = /bits/ 8 <127 255>;
 306         };
 307         fan@5 {
 308                 reg = <0x05>;
 309                 fan-tach-ch = /bits/ 8 <0x0A 0x0B>;
 310                 cooling-levels = /bits/ 8 <127 255>;
 311         };
 312         fan@6 {
 313                 reg = <0x06>;
 314                 fan-tach-ch = /bits/ 8 <0x0C 0x0D>;
 315                 cooling-levels = /bits/ 8 <127 255>;
 316         };
 317         fan@7 {
 318                 reg = <0x07>;
 319                 fan-tach-ch = /bits/ 8 <0x0E 0x0F>;
 320                 cooling-levels = /bits/ 8 <127 255>;
 321         };
 322 };
 323
 324 &spi0 {
 325         cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
 326         status = "okay";
 327         Flash@0 {
 328                 compatible = "winbond,w25q128",
 329                 "jedec,spi-nor";
 330                 reg = <0x0>;
 331                 #address-cells = <1>;
 332                 #size-cells = <1>;
 333                 spi-max-frequency = <5000000>;
 334                 partition@0 {
 335                         label = "spi0_spare1";
 336                         reg = <0x0000000 0x800000>;
 337                 };
 338                 partition@1 {
 339                         label = "spi0_spare2";
 340                         reg = <0x800000 0x0>;
 341                 };
 342         };
 343 };
 344
 345 &spi1 {
 346         cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
 347         status = "okay";
 348         Flash@0 {
 349                 compatible = "winbond,w25q128fw",
 350                 "jedec,spi-nor";
 351                 reg = <0x0>;
 352                 #address-cells = <1>;
 353                 #size-cells = <1>;
 354                 spi-max-frequency = <5000000>;
 355                 partition@0 {
 356                         label = "spi1_spare1";
 357                         reg = <0x0000000 0x800000>;
 358                 };
 359                 partition@1 {
 360                         label = "spi1_spare2";
 361                         reg = <0x800000 0x0>;
 362                 };
 363         };
 364 };
 365
 366 &pinctrl {
 367         pinctrl-names = "default";
 368         pinctrl-0 = <   &iox1_pins
 369                         &pin8_input
 370                         &pin9_output_high
 371                         &pin10_input
 372                         &pin11_output_high
 373                         &pin16_input
 374                         &pin24_output_high
 375                         &pin25_output_low
 376                         &pin32_output_high
 377                         &jtag2_pins
 378                         &pin61_output_high
 379                         &pin62_output_high
 380                         &pin63_output_high
 381                         &lpc_pins
 382                         &pin160_input
 383                         &pin162_input
 384                         &pin168_input
 385                         &pin169_input
 386                         &pin170_input
 387                         &pin187_output_high
 388                         &pin190_input
 389                         &pin191_output_high
 390                         &pin192_output_high
 391                         &pin197_output_low
 392                         &ddc_pins
 393                         &pin218_input
 394                         &pin219_output_low
 395                         &pin220_output_low
 396                         &pin221_output_high
 397                         &pin222_input
 398                         &pin223_output_low
 399                         &spix_pins
 400                         &pin228_output_low
 401                         &pin231_output_high
 402                         &pin255_input>;
 403 };
 404