2 * Device Tree Source for OMAP2420 SoC
4 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
14 compatible = "ti,omap2420", "ti,omap2";
18 compatible = "ti,omap2-l4", "simple-bus";
21 ranges = <0 0x48000000 0x100000>;
24 compatible = "ti,omap2-prcm";
25 reg = <0x8000 0x1000>;
32 prcm_clockdomains: clockdomains {
37 compatible = "ti,omap2-scm", "simple-bus";
42 ranges = <0 0x0 0x1000>;
44 omap2420_pmx: pinmux@30 {
45 compatible = "ti,omap2420-padconf",
51 pinctrl-single,register-width = <8>;
52 pinctrl-single,function-mask = <0x3f>;
55 scm_conf: scm_conf@270 {
56 compatible = "syscon";
67 scm_clockdomains: clockdomains {
72 compatible = "ti,sysc-omap2", "ti,sysc";
75 reg-names = "rev", "sysc";
76 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
78 clocks = <&func_32k_ck>;
82 ranges = <0x0 0x4000 0x1000>;
84 counter32k: counter@0 {
85 compatible = "ti,omap-counter32k";
91 gpio1: gpio@48018000 {
92 compatible = "ti,omap2-gpio";
93 reg = <0x48018000 0x200>;
99 #interrupt-cells = <2>;
100 interrupt-controller;
103 gpio2: gpio@4801a000 {
104 compatible = "ti,omap2-gpio";
105 reg = <0x4801a000 0x200>;
111 #interrupt-cells = <2>;
112 interrupt-controller;
115 gpio3: gpio@4801c000 {
116 compatible = "ti,omap2-gpio";
117 reg = <0x4801c000 0x200>;
123 #interrupt-cells = <2>;
124 interrupt-controller;
127 gpio4: gpio@4801e000 {
128 compatible = "ti,omap2-gpio";
129 reg = <0x4801e000 0x200>;
135 #interrupt-cells = <2>;
136 interrupt-controller;
139 gpmc: gpmc@6800a000 {
140 compatible = "ti,omap2420-gpmc";
141 reg = <0x6800a000 0x1000>;
142 #address-cells = <2>;
146 gpmc,num-waitpins = <4>;
148 interrupt-controller;
149 #interrupt-cells = <2>;
154 mcbsp1: mcbsp@48074000 {
155 compatible = "ti,omap2420-mcbsp";
156 reg = <0x48074000 0xff>;
158 interrupts = <59>, /* TX interrupt */
159 <60>; /* RX interrupt */
160 interrupt-names = "tx", "rx";
161 ti,hwmods = "mcbsp1";
164 dma-names = "tx", "rx";
168 mcbsp2: mcbsp@48076000 {
169 compatible = "ti,omap2420-mcbsp";
170 reg = <0x48076000 0xff>;
172 interrupts = <62>, /* TX interrupt */
173 <63>; /* RX interrupt */
174 interrupt-names = "tx", "rx";
175 ti,hwmods = "mcbsp2";
178 dma-names = "tx", "rx";
182 msdi1: mmc@4809c000 {
183 compatible = "ti,omap2420-mmc";
185 reg = <0x4809c000 0x80>;
187 dmas = <&sdma 61 &sdma 62>;
188 dma-names = "tx", "rx";
191 mailbox: mailbox@48094000 {
192 compatible = "ti,omap2-mailbox";
193 reg = <0x48094000 0x200>;
194 interrupts = <26>, <34>;
195 interrupt-names = "dsp", "iva";
196 ti,hwmods = "mailbox";
198 ti,mbox-num-users = <4>;
199 ti,mbox-num-fifos = <6>;
201 ti,mbox-tx = <0 0 0>;
202 ti,mbox-rx = <1 0 0>;
205 ti,mbox-tx = <2 1 3>;
206 ti,mbox-rx = <3 1 3>;
210 timer1_target: target-module@48028000 {
211 compatible = "ti,sysc-omap2-timer", "ti,sysc";
212 reg = <0x48028000 0x4>,
215 reg-names = "rev", "sysc", "syss";
216 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
218 SYSC_OMAP2_ENAWAKEUP |
219 SYSC_OMAP2_SOFTRESET |
220 SYSC_OMAP2_AUTOIDLE)>;
221 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
225 clocks = <&gpt1_fck>, <&gpt1_ick>;
226 clock-names = "fck", "ick";
227 #address-cells = <1>;
229 ranges = <0x0 0x48028000 0x1000>;
232 compatible = "ti,omap2420-timer";
239 wd_timer2: wdt@48022000 {
240 compatible = "ti,omap2-wdt";
241 ti,hwmods = "wd_timer2";
242 reg = <0x48022000 0x80>;
248 compatible = "ti,omap2420-i2c";
252 compatible = "ti,omap2420-i2c";
255 #include "omap24xx-clocks.dtsi"
256 #include "omap2420-clocks.dtsi"
258 /* Preferred always-on timer for clockevent */
263 assigned-clocks = <&gpt1_fck>;
264 assigned-clock-parents = <&func_32k_ck>;