| blob | a03bca5a358441c5977f1f8ae3ef697aac1caea2 |
1 &l4_abe { /* 0x40100000 */
2 compatible = "ti,omap5-l4-abe", "simple-pm-bus";
3 reg = <0x40100000 0x400>,
4 <0x40100400 0x400>;
5 reg-names = "la", "ap";
6 power-domains = <&prm_abe>;
7 /* OMAP5_L4_ABE_CLKCTRL is read-only */
8 #address-cells = <1>;
9 #size-cells = <1>;
10 ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
11 <0x49000000 0x49000000 0x100000>;
12 segment@0 { /* 0x40100000 */
13 compatible = "simple-pm-bus";
14 #address-cells = <1>;
15 #size-cells = <1>;
16 ranges =
17 /* CPU to L4 ABE mapping */
18 <0x00000000 0x00000000 0x000400>, /* ap 0 */
19 <0x00000400 0x00000400 0x000400>, /* ap 1 */
20 <0x00022000 0x00022000 0x001000>, /* ap 2 */
21 <0x00023000 0x00023000 0x001000>, /* ap 3 */
22 <0x00024000 0x00024000 0x001000>, /* ap 4 */
23 <0x00025000 0x00025000 0x001000>, /* ap 5 */
24 <0x00026000 0x00026000 0x001000>, /* ap 6 */
25 <0x00027000 0x00027000 0x001000>, /* ap 7 */
26 <0x00028000 0x00028000 0x001000>, /* ap 8 */
27 <0x00029000 0x00029000 0x001000>, /* ap 9 */
28 <0x0002a000 0x0002a000 0x001000>, /* ap 10 */
29 <0x0002b000 0x0002b000 0x001000>, /* ap 11 */
30 <0x0002e000 0x0002e000 0x001000>, /* ap 12 */
31 <0x0002f000 0x0002f000 0x001000>, /* ap 13 */
32 <0x00030000 0x00030000 0x001000>, /* ap 14 */
33 <0x00031000 0x00031000 0x001000>, /* ap 15 */
34 <0x00032000 0x00032000 0x001000>, /* ap 16 */
35 <0x00033000 0x00033000 0x001000>, /* ap 17 */
36 <0x00038000 0x00038000 0x001000>, /* ap 18 */
37 <0x00039000 0x00039000 0x001000>, /* ap 19 */
38 <0x0003a000 0x0003a000 0x001000>, /* ap 20 */
39 <0x0003b000 0x0003b000 0x001000>, /* ap 21 */
40 <0x0003c000 0x0003c000 0x001000>, /* ap 22 */
41 <0x0003d000 0x0003d000 0x001000>, /* ap 23 */
42 <0x0003e000 0x0003e000 0x001000>, /* ap 24 */
43 <0x0003f000 0x0003f000 0x001000>, /* ap 25 */
44 <0x00080000 0x00080000 0x010000>, /* ap 26 */
45 <0x00080000 0x00080000 0x001000>, /* ap 27 */
46 <0x000a0000 0x000a0000 0x010000>, /* ap 28 */
47 <0x000a0000 0x000a0000 0x001000>, /* ap 29 */
48 <0x000c0000 0x000c0000 0x010000>, /* ap 30 */
49 <0x000c0000 0x000c0000 0x001000>, /* ap 31 */
50 <0x000f1000 0x000f1000 0x001000>, /* ap 32 */
51 <0x000f2000 0x000f2000 0x001000>, /* ap 33 */
53 /* L3 to L4 ABE mapping */
54 <0x49000000 0x49000000 0x000400>, /* ap 0 */
55 <0x49000400 0x49000400 0x000400>, /* ap 1 */
56 <0x49022000 0x49022000 0x001000>, /* ap 2 */
57 <0x49023000 0x49023000 0x001000>, /* ap 3 */
58 <0x49024000 0x49024000 0x001000>, /* ap 4 */
59 <0x49025000 0x49025000 0x001000>, /* ap 5 */
60 <0x49026000 0x49026000 0x001000>, /* ap 6 */
61 <0x49027000 0x49027000 0x001000>, /* ap 7 */
62 <0x49028000 0x49028000 0x001000>, /* ap 8 */
63 <0x49029000 0x49029000 0x001000>, /* ap 9 */
64 <0x4902a000 0x4902a000 0x001000>, /* ap 10 */
65 <0x4902b000 0x4902b000 0x001000>, /* ap 11 */
66 <0x4902e000 0x4902e000 0x001000>, /* ap 12 */
67 <0x4902f000 0x4902f000 0x001000>, /* ap 13 */
68 <0x49030000 0x49030000 0x001000>, /* ap 14 */
69 <0x49031000 0x49031000 0x001000>, /* ap 15 */
70 <0x49032000 0x49032000 0x001000>, /* ap 16 */
71 <0x49033000 0x49033000 0x001000>, /* ap 17 */
72 <0x49038000 0x49038000 0x001000>, /* ap 18 */
73 <0x49039000 0x49039000 0x001000>, /* ap 19 */
74 <0x4903a000 0x4903a000 0x001000>, /* ap 20 */
75 <0x4903b000 0x4903b000 0x001000>, /* ap 21 */
76 <0x4903c000 0x4903c000 0x001000>, /* ap 22 */
77 <0x4903d000 0x4903d000 0x001000>, /* ap 23 */
78 <0x4903e000 0x4903e000 0x001000>, /* ap 24 */
79 <0x4903f000 0x4903f000 0x001000>, /* ap 25 */
80 <0x49080000 0x49080000 0x010000>, /* ap 26 */
81 <0x49080000 0x49080000 0x001000>, /* ap 27 */
82 <0x490a0000 0x490a0000 0x010000>, /* ap 28 */
83 <0x490a0000 0x490a0000 0x001000>, /* ap 29 */
84 <0x490c0000 0x490c0000 0x010000>, /* ap 30 */
85 <0x490c0000 0x490c0000 0x001000>, /* ap 31 */
86 <0x490f1000 0x490f1000 0x001000>, /* ap 32 */
87 <0x490f2000 0x490f2000 0x001000>; /* ap 33 */
89 target-module@22000 { /* 0x40122000, ap 2 02.0 */
90 compatible = "ti,sysc-omap2", "ti,sysc";
91 reg = <0x2208c 0x4>;
92 reg-names = "sysc";
93 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
94 SYSC_OMAP2_ENAWAKEUP |
95 SYSC_OMAP2_SOFTRESET)>;
96 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
97 <SYSC_IDLE_NO>,
98 <SYSC_IDLE_SMART>;
99 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
100 clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 0>;
101 clock-names = "fck";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 ranges = <0x0 0x22000 0x1000>,
105 <0x49022000 0x49022000 0x1000>;
107 mcbsp1: mcbsp@0 {
108 compatible = "ti,omap4-mcbsp";
109 reg = <0x0 0xff>, /* MPU private access */
110 <0x49022000 0xff>; /* L3 Interconnect */
111 reg-names = "mpu", "dma";
112 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
113 interrupt-names = "common";
114 ti,buffer-size = <128>;
115 dmas = <&sdma 33>,
116 <&sdma 34>;
117 dma-names = "tx", "rx";
118 status = "disabled";
119 };
120 };
122 target-module@24000 { /* 0x40124000, ap 4 04.0 */
123 compatible = "ti,sysc-omap2", "ti,sysc";
124 reg = <0x2408c 0x4>;
125 reg-names = "sysc";
126 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
127 SYSC_OMAP2_ENAWAKEUP |
128 SYSC_OMAP2_SOFTRESET)>;
129 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
130 <SYSC_IDLE_NO>,
131 <SYSC_IDLE_SMART>;
132 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
133 clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 0>;
134 clock-names = "fck";
135 #address-cells = <1>;
136 #size-cells = <1>;
137 ranges = <0x0 0x24000 0x1000>,
138 <0x49024000 0x49024000 0x1000>;
140 mcbsp2: mcbsp@0 {
141 compatible = "ti,omap4-mcbsp";
142 reg = <0x0 0xff>, /* MPU private access */
143 <0x49024000 0xff>; /* L3 Interconnect */
144 reg-names = "mpu", "dma";
145 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
146 interrupt-names = "common";
147 ti,buffer-size = <128>;
148 dmas = <&sdma 17>,
149 <&sdma 18>;
150 dma-names = "tx", "rx";
151 status = "disabled";
152 };
153 };
155 target-module@26000 { /* 0x40126000, ap 6 06.0 */
156 compatible = "ti,sysc-omap2", "ti,sysc";
157 reg = <0x2608c 0x4>;
158 reg-names = "sysc";
159 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
160 SYSC_OMAP2_ENAWAKEUP |
161 SYSC_OMAP2_SOFTRESET)>;
162 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
163 <SYSC_IDLE_NO>,
164 <SYSC_IDLE_SMART>;
165 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
166 clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 0>;
167 clock-names = "fck";
168 #address-cells = <1>;
169 #size-cells = <1>;
170 ranges = <0x0 0x26000 0x1000>,
171 <0x49026000 0x49026000 0x1000>;
173 mcbsp3: mcbsp@0 {
174 compatible = "ti,omap4-mcbsp";
175 reg = <0x0 0xff>, /* MPU private access */
176 <0x49026000 0xff>; /* L3 Interconnect */
177 reg-names = "mpu", "dma";
178 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
179 interrupt-names = "common";
180 ti,buffer-size = <128>;
181 dmas = <&sdma 19>,
182 <&sdma 20>;
183 dma-names = "tx", "rx";
184 status = "disabled";
185 };
186 };
188 target-module@28000 { /* 0x40128000, ap 8 08.0 */
189 compatible = "ti,sysc";
190 status = "disabled";
191 #address-cells = <1>;
192 #size-cells = <1>;
193 ranges = <0x0 0x28000 0x1000>,
194 <0x49028000 0x49028000 0x1000>;
195 };
197 target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */
198 compatible = "ti,sysc";
199 status = "disabled";
200 #address-cells = <1>;
201 #size-cells = <1>;
202 ranges = <0x0 0x2a000 0x1000>,
203 <0x4902a000 0x4902a000 0x1000>;
204 };
206 target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */
207 compatible = "ti,sysc-omap4", "ti,sysc";
208 reg = <0x2e000 0x4>,
209 <0x2e010 0x4>;
210 reg-names = "rev", "sysc";
211 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
212 SYSC_OMAP4_SOFTRESET)>;
213 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
214 <SYSC_IDLE_NO>,
215 <SYSC_IDLE_SMART>,
216 <SYSC_IDLE_SMART_WKUP>;
217 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
218 clocks = <&abe_clkctrl OMAP5_DMIC_CLKCTRL 0>;
219 clock-names = "fck";
220 #address-cells = <1>;
221 #size-cells = <1>;
222 ranges = <0x0 0x2e000 0x1000>,
223 <0x4902e000 0x4902e000 0x1000>;
225 dmic: dmic@0 {
226 compatible = "ti,omap4-dmic";
227 reg = <0x0 0x7f>, /* MPU private access */
228 <0x4902e000 0x7f>; /* L3 Interconnect */
229 reg-names = "mpu", "dma";
230 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
231 dmas = <&sdma 67>;
232 dma-names = "up_link";
233 status = "disabled";
234 };
235 };
237 target-module@30000 { /* 0x40130000, ap 14 0e.0 */
238 compatible = "ti,sysc";
239 status = "disabled";
240 #address-cells = <1>;
241 #size-cells = <1>;
242 ranges = <0x0 0x30000 0x1000>,
243 <0x49030000 0x49030000 0x1000>;
244 };
246 mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */
247 compatible = "ti,sysc-omap4", "ti,sysc";
248 reg = <0x32000 0x4>,
249 <0x32010 0x4>;
250 reg-names = "rev", "sysc";
251 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
252 SYSC_OMAP4_SOFTRESET)>;
253 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
254 <SYSC_IDLE_NO>,
255 <SYSC_IDLE_SMART>,
256 <SYSC_IDLE_SMART_WKUP>;
257 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
258 clocks = <&abe_clkctrl OMAP5_MCPDM_CLKCTRL 0>;
259 clock-names = "fck";
260 #address-cells = <1>;
261 #size-cells = <1>;
262 ranges = <0x0 0x32000 0x1000>,
263 <0x49032000 0x49032000 0x1000>;
265 /* Must be only enabled for boards with pdmclk wired */
266 status = "disabled";
268 mcpdm: mcpdm@0 {
269 compatible = "ti,omap4-mcpdm";
270 reg = <0x0 0x7f>, /* MPU private access */
271 <0x49032000 0x7f>; /* L3 Interconnect */
272 reg-names = "mpu", "dma";
273 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
274 dmas = <&sdma 65>,
275 <&sdma 66>;
276 dma-names = "up_link", "dn_link";
277 };
278 };
280 target-module@38000 { /* 0x40138000, ap 18 12.0 */
281 compatible = "ti,sysc-omap4-timer", "ti,sysc";
282 reg = <0x38000 0x4>,
283 <0x38010 0x4>;
284 reg-names = "rev", "sysc";
285 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
286 SYSC_OMAP4_SOFTRESET)>;
287 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
288 <SYSC_IDLE_NO>,
289 <SYSC_IDLE_SMART>,
290 <SYSC_IDLE_SMART_WKUP>;
291 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
292 clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 0>;
293 clock-names = "fck";
294 #address-cells = <1>;
295 #size-cells = <1>;
296 ranges = <0x0 0x38000 0x1000>,
297 <0x49038000 0x49038000 0x1000>;
299 timer5: timer@0 {
300 compatible = "ti,omap5430-timer";
301 reg = <0x0 0x80>,
302 <0x49038000 0x80>;
303 clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>,
304 <&dss_syc_gfclk_div>;
305 clock-names = "fck", "timer_sys_ck";
306 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
307 ti,timer-dsp;
308 ti,timer-pwm;
309 };
310 };
312 target-module@3a000 { /* 0x4013a000, ap 20 14.0 */
313 compatible = "ti,sysc-omap4-timer", "ti,sysc";
314 reg = <0x3a000 0x4>,
315 <0x3a010 0x4>;
316 reg-names = "rev", "sysc";
317 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
318 SYSC_OMAP4_SOFTRESET)>;
319 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
320 <SYSC_IDLE_NO>,
321 <SYSC_IDLE_SMART>,
322 <SYSC_IDLE_SMART_WKUP>;
323 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
324 clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 0>;
325 clock-names = "fck";
326 #address-cells = <1>;
327 #size-cells = <1>;
328 ranges = <0x0 0x3a000 0x1000>,
329 <0x4903a000 0x4903a000 0x1000>;
331 timer6: timer@0 {
332 compatible = "ti,omap5430-timer";
333 reg = <0x0 0x80>,
334 <0x4903a000 0x80>;
335 clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>,
336 <&dss_syc_gfclk_div>;
337 clock-names = "fck", "timer_sys_ck";
338 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
339 ti,timer-dsp;
340 ti,timer-pwm;
341 };
342 };
344 target-module@3c000 { /* 0x4013c000, ap 22 16.0 */
345 compatible = "ti,sysc-omap4-timer", "ti,sysc";
346 reg = <0x3c000 0x4>,
347 <0x3c010 0x4>;
348 reg-names = "rev", "sysc";
349 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
350 SYSC_OMAP4_SOFTRESET)>;
351 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
352 <SYSC_IDLE_NO>,
353 <SYSC_IDLE_SMART>,
354 <SYSC_IDLE_SMART_WKUP>;
355 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
356 clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 0>;
357 clock-names = "fck";
358 #address-cells = <1>;
359 #size-cells = <1>;
360 ranges = <0x0 0x3c000 0x1000>,
361 <0x4903c000 0x4903c000 0x1000>;
363 timer7: timer@0 {
364 compatible = "ti,omap5430-timer";
365 reg = <0x0 0x80>,
366 <0x4903c000 0x80>;
367 clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>,
368 <&dss_syc_gfclk_div>;
369 clock-names = "fck", "timer_sys_ck";
370 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
371 ti,timer-dsp;
372 };
373 };
375 target-module@3e000 { /* 0x4013e000, ap 24 18.0 */
376 compatible = "ti,sysc-omap4-timer", "ti,sysc";
377 reg = <0x3e000 0x4>,
378 <0x3e010 0x4>;
379 reg-names = "rev", "sysc";
380 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
381 SYSC_OMAP4_SOFTRESET)>;
382 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
383 <SYSC_IDLE_NO>,
384 <SYSC_IDLE_SMART>,
385 <SYSC_IDLE_SMART_WKUP>;
386 /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
387 clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 0>;
388 clock-names = "fck";
389 #address-cells = <1>;
390 #size-cells = <1>;
391 ranges = <0x0 0x3e000 0x1000>,
392 <0x4903e000 0x4903e000 0x1000>;
394 timer8: timer@0 {
395 compatible = "ti,omap5430-timer";
396 reg = <0x0 0x80>,
397 <0x4903e000 0x80>;
398 clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>,
399 <&dss_syc_gfclk_div>;
400 clock-names = "fck", "timer_sys_ck";
401 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
402 ti,timer-dsp;
403 ti,timer-pwm;
404 };
405 };
407 target-module@80000 { /* 0x40180000, ap 26 1a.0 */
408 compatible = "ti,sysc";
409 status = "disabled";
410 #address-cells = <1>;
411 #size-cells = <1>;
412 ranges = <0x0 0x80000 0x10000>,
413 <0x49080000 0x49080000 0x10000>;
414 };
416 target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */
417 compatible = "ti,sysc";
418 status = "disabled";
419 #address-cells = <1>;
420 #size-cells = <1>;
421 ranges = <0x0 0xa0000 0x10000>,
422 <0x490a0000 0x490a0000 0x10000>;
423 };
425 target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */
426 compatible = "ti,sysc";
427 status = "disabled";
428 #address-cells = <1>;
429 #size-cells = <1>;
430 ranges = <0x0 0xc0000 0x10000>,
431 <0x490c0000 0x490c0000 0x10000>;
432 };
434 target-module@f1000 { /* 0x401f1000, ap 32 20.0 */
435 compatible = "ti,sysc-omap4", "ti,sysc";
436 reg = <0xf1000 0x4>,
437 <0xf1010 0x4>;
438 reg-names = "rev", "sysc";
439 ti,sysc-midle = <SYSC_IDLE_FORCE>,
440 <SYSC_IDLE_NO>,
441 <SYSC_IDLE_SMART>,
442 <SYSC_IDLE_SMART_WKUP>;
443 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
444 <SYSC_IDLE_NO>,
445 <SYSC_IDLE_SMART>;
446 /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
447 clocks = <&abe_clkctrl OMAP5_AESS_CLKCTRL 0>;
448 clock-names = "fck";
449 #address-cells = <1>;
450 #size-cells = <1>;
451 ranges = <0x0 0xf1000 0x1000>,
452 <0x490f1000 0x490f1000 0x1000>;
453 };
454 };
455 };