arch/arm/boot/dts/owl-s500.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Actions Semi S500 SoC
   4  *
   5  * Copyright (c) 2016-2017 Andreas Färber
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/power/owl-s500-powergate.h>
  10
  11 / {
  12         compatible = "actions,s500";
  13         interrupt-parent = <&gic>;
  14         #address-cells = <1>;
  15         #size-cells = <1>;
  16
  17         aliases {
  18         };
  19
  20         chosen {
  21         };
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26
  27                 cpu0: cpu@0 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a9";
  30                         reg = <0x0>;
  31                         enable-method = "actions,s500-smp";
  32                 };
  33
  34                 cpu1: cpu@1 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a9";
  37                         reg = <0x1>;
  38                         enable-method = "actions,s500-smp";
  39                 };
  40
  41                 cpu2: cpu@2 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a9";
  44                         reg = <0x2>;
  45                         enable-method = "actions,s500-smp";
  46                         power-domains = <&sps S500_PD_CPU2>;
  47                 };
  48
  49                 cpu3: cpu@3 {
  50                         device_type = "cpu";
  51                         compatible = "arm,cortex-a9";
  52                         reg = <0x3>;
  53                         enable-method = "actions,s500-smp";
  54                         power-domains = <&sps S500_PD_CPU3>;
  55                 };
  56         };
  57
  58         arm-pmu {
  59                 compatible = "arm,cortex-a9-pmu";
  60                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
  61                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
  62                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  63                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  64                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  65         };
  66
  67         hosc: hosc {
  68                 compatible = "fixed-clock";
  69                 clock-frequency = <24000000>;
  70                 #clock-cells = <0>;
  71         };
  72
  73         soc {
  74                 compatible = "simple-bus";
  75                 #address-cells = <1>;
  76                 #size-cells = <1>;
  77                 ranges;
  78
  79                 scu: scu@b0020000 {
  80                         compatible = "arm,cortex-a9-scu";
  81                         reg = <0xb0020000 0x100>;
  82                 };
  83
  84                 global_timer: timer@b0020200 {
  85                         compatible = "arm,cortex-a9-global-timer";
  86                         reg = <0xb0020200 0x100>;
  87                         interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
  88                         status = "disabled";
  89                 };
  90
  91                 twd_timer: timer@b0020600 {
  92                         compatible = "arm,cortex-a9-twd-timer";
  93                         reg = <0xb0020600 0x20>;
  94                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
  95                         status = "disabled";
  96                 };
  97
  98                 twd_wdt: wdt@b0020620 {
  99                         compatible = "arm,cortex-a9-twd-wdt";
 100                         reg = <0xb0020620 0xe0>;
 101                         interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 102                         status = "disabled";
 103                 };
 104
 105                 gic: interrupt-controller@b0021000 {
 106                         compatible = "arm,cortex-a9-gic";
 107                         reg = <0xb0021000 0x1000>,
 108                               <0xb0020100 0x0100>;
 109                         interrupt-controller;
 110                         #interrupt-cells = <3>;
 111                 };
 112
 113                 l2: cache-controller@b0022000 {
 114                         compatible = "arm,pl310-cache";
 115                         reg = <0xb0022000 0x1000>;
 116                         cache-unified;
 117                         cache-level = <2>;
 118                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 119                         arm,tag-latency = <3 3 2>;
 120                         arm,data-latency = <5 3 3>;
 121                 };
 122
 123                 uart0: serial@b0120000 {
 124                         compatible = "actions,s500-uart", "actions,owl-uart";
 125                         reg = <0xb0120000 0x2000>;
 126                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 127                         status = "disabled";
 128                 };
 129
 130                 uart1: serial@b0122000 {
 131                         compatible = "actions,s500-uart", "actions,owl-uart";
 132                         reg = <0xb0122000 0x2000>;
 133                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 134                         status = "disabled";
 135                 };
 136
 137                 uart2: serial@b0124000 {
 138                         compatible = "actions,s500-uart", "actions,owl-uart";
 139                         reg = <0xb0124000 0x2000>;
 140                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 141                         status = "disabled";
 142                 };
 143
 144                 uart3: serial@b0126000 {
 145                         compatible = "actions,s500-uart", "actions,owl-uart";
 146                         reg = <0xb0126000 0x2000>;
 147                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 148                         status = "disabled";
 149                 };
 150
 151                 uart4: serial@b0128000 {
 152                         compatible = "actions,s500-uart", "actions,owl-uart";
 153                         reg = <0xb0128000 0x2000>;
 154                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 155                         status = "disabled";
 156                 };
 157
 158                 uart5: serial@b012a000 {
 159                         compatible = "actions,s500-uart", "actions,owl-uart";
 160                         reg = <0xb012a000 0x2000>;
 161                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 162                         status = "disabled";
 163                 };
 164
 165                 uart6: serial@b012c000 {
 166                         compatible = "actions,s500-uart", "actions,owl-uart";
 167                         reg = <0xb012c000 0x2000>;
 168                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 169                         status = "disabled";
 170                 };
 171
 172                 timer: timer@b0168000 {
 173                         compatible = "actions,s500-timer";
 174                         reg = <0xb0168000 0x8000>;
 175                         interrupts = <GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
 176                                      <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
 177                                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 178                                      <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 179                         interrupt-names = "2hz0", "2hz1", "timer0", "timer1";
 180                 };
 181
 182                 sps: power-controller@b01b0100 {
 183                         compatible = "actions,s500-sps";
 184                         reg = <0xb01b0100 0x100>;
 185                         #power-domain-cells = <1>;
 186                 };
 187         };
 188 };