arch/arm/boot/dts/r7s72100-gr-peach.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the GR-Peach board
   4  *
   5  * Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org>
   6  * Copyright (C) 2016 Renesas Electronics
   7  */
   8
   9 /dts-v1/;
  10 #include "r7s72100.dtsi"
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
  13
  14 / {
  15         model = "GR-Peach";
  16         compatible = "renesas,gr-peach", "renesas,r7s72100";
  17
  18         aliases {
  19                 serial0 = &scif2;
  20         };
  21
  22         chosen {
  23                 bootargs = "ignore_loglevel rw root=/dev/mtdblock0";
  24                 stdout-path = "serial0:115200n8";
  25         };
  26
  27         memory@20000000 {
  28                 device_type = "memory";
  29                 reg = <0x20000000 0x00a00000>;
  30         };
  31
  32         lbsc {
  33                 #address-cells = <1>;
  34                 #size-cells = <1>;
  35         };
  36
  37         flash@18000000 {
  38                 compatible = "mtd-rom";
  39                 probe-type = "map_rom";
  40                 reg = <0x18000000 0x00800000>;
  41                 bank-width = <4>;
  42                 device-width = <1>;
  43
  44                 clocks = <&mstp9_clks R7S72100_CLK_SPIBSC0>;
  45                 power-domains = <&cpg_clocks>;
  46
  47                 #address-cells = <1>;
  48                 #size-cells = <1>;
  49
  50                 rootfs@600000 {
  51                         label = "rootfs";
  52                         reg = <0x00600000 0x00200000>;
  53                 };
  54         };
  55
  56         leds {
  57                 status = "okay";
  58                 compatible = "gpio-leds";
  59
  60                 led1 {
  61                         gpios = <&port6 12 GPIO_ACTIVE_HIGH>;
  62                 };
  63         };
  64 };
  65
  66 &pinctrl {
  67         scif2_pins: serial2 {
  68                 /* P6_2 as RxD2; P6_3 as TxD2 */
  69                 pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>;
  70         };
  71
  72         ether_pins: ether {
  73                 /* Ethernet on Ports 1,3,5,10 */
  74                 pinmux = <RZA1_PINMUX(1, 14, 4)>, /* P1_14 = ET_COL   */
  75                          <RZA1_PINMUX(3, 0, 2)>,  /* P3_0 = ET_TXCLK  */
  76                          <RZA1_PINMUX(3, 3, 2)>,  /* P3_3 = ET_MDIO   */
  77                          <RZA1_PINMUX(3, 4, 2)>,  /* P3_4 = ET_RXCLK  */
  78                          <RZA1_PINMUX(3, 5, 2)>,  /* P3_5 = ET_RXER   */
  79                          <RZA1_PINMUX(3, 6, 2)>,  /* P3_6 = ET_RXDV   */
  80                          <RZA1_PINMUX(5, 9, 2)>,  /* P5_9 = ET_MDC    */
  81                          <RZA1_PINMUX(10, 1, 4)>, /* P10_1 = ET_TXER  */
  82                          <RZA1_PINMUX(10, 2, 4)>, /* P10_2 = ET_TXEN  */
  83                          <RZA1_PINMUX(10, 3, 4)>, /* P10_3 = ET_CRS   */
  84                          <RZA1_PINMUX(10, 4, 4)>, /* P10_4 = ET_TXD0  */
  85                          <RZA1_PINMUX(10, 5, 4)>, /* P10_5 = ET_TXD1  */
  86                          <RZA1_PINMUX(10, 6, 4)>, /* P10_6 = ET_TXD2  */
  87                          <RZA1_PINMUX(10, 7, 4)>, /* P10_7 = ET_TXD3  */
  88                          <RZA1_PINMUX(10, 8, 4)>, /* P10_8 = ET_RXD0  */
  89                          <RZA1_PINMUX(10, 9, 4)>, /* P10_9 = ET_RXD1  */
  90                          <RZA1_PINMUX(10, 10, 4)>,/* P10_10 = ET_RXD2 */
  91                          <RZA1_PINMUX(10, 11, 4)>;/* P10_11 = ET_RXD3 */
  92         };
  93 };
  94
  95 &extal_clk {
  96         clock-frequency = <13333000>;
  97 };
  98
  99 &usb_x1_clk {
 100         clock-frequency = <48000000>;
 101 };
 102
 103 &mtu2 {
 104         status = "okay";
 105 };
 106
 107 &ostm0 {
 108         status = "okay";
 109 };
 110
 111 &ostm1 {
 112         status = "okay";
 113 };
 114
 115 &scif2 {
 116         pinctrl-names = "default";
 117         pinctrl-0 = <&scif2_pins>;
 118
 119         status = "okay";
 120 };
 121
 122 &ether {
 123         pinctrl-names = "default";
 124         pinctrl-0 = <&ether_pins>;
 125
 126         status = "okay";
 127
 128         renesas,no-ether-link;
 129         phy-handle = <&phy0>;
 130
 131         phy0: ethernet-phy@0 {
 132                 reg = <0>;
 133
 134                 reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
 135                 reset-delay-us = <5>;
 136         };
 137 };