arch/arm/boot/dts/rk3288-veyron-minnie.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Google Veyron Minnie Rev 0+ board device tree source
   4  *
   5  * Copyright 2015 Google, Inc
   6  */
   7
   8 /dts-v1/;
   9 #include "rk3288-veyron-chromebook.dtsi"
  10 #include "rk3288-veyron-broadcom-bluetooth.dtsi"
  11
  12 / {
  13         model = "Google Minnie";
  14         compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3",
  15                      "google,veyron-minnie-rev2", "google,veyron-minnie-rev1",
  16                      "google,veyron-minnie-rev0", "google,veyron-minnie",
  17                      "google,veyron", "rockchip,rk3288";
  18
  19         volume_buttons: volume-buttons {
  20                 compatible = "gpio-keys";
  21                 pinctrl-names = "default";
  22                 pinctrl-0 = <&volum_down_l &volum_up_l>;
  23
  24                 volum_down {
  25                         label = "Volum_down";
  26                         gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>;
  27                         linux,code = <KEY_VOLUMEDOWN>;
  28                         debounce-interval = <100>;
  29                 };
  30
  31                 volum_up {
  32                         label = "Volum_up";
  33                         gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>;
  34                         linux,code = <KEY_VOLUMEUP>;
  35                         debounce-interval = <100>;
  36                 };
  37         };
  38 };
  39
  40 &backlight {
  41         /* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */
  42         brightness-levels = <3 255>;
  43         num-interpolated-steps = <252>;
  44 };
  45
  46 &i2c_tunnel {
  47         battery: bq27500@55 {
  48                 compatible = "ti,bq27500";
  49                 reg = <0x55>;
  50         };
  51 };
  52
  53 &i2c3 {
  54         status = "okay";
  55
  56         clock-frequency = <400000>;
  57         i2c-scl-falling-time-ns = <50>;
  58         i2c-scl-rising-time-ns = <300>;
  59
  60         touchscreen@10 {
  61                 compatible = "elan,ekth3500";
  62                 reg = <0x10>;
  63                 interrupt-parent = <&gpio2>;
  64                 interrupts = <RK_PB6 IRQ_TYPE_EDGE_FALLING>;
  65                 pinctrl-names = "default";
  66                 pinctrl-0 = <&touch_int &touch_rst>;
  67                 reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>;
  68                 vcc33-supply = <&vcc33_touch>;
  69                 vccio-supply = <&vcc33_touch>;
  70         };
  71 };
  72
  73 &panel {
  74         compatible = "auo,b101ean01";
  75
  76         /delete-node/ panel-timing;
  77
  78         panel-timing {
  79                 clock-frequency = <66666667>;
  80                 hactive = <1280>;
  81                 hfront-porch = <18>;
  82                 hback-porch = <21>;
  83                 hsync-len = <32>;
  84                 vactive = <800>;
  85                 vfront-porch = <4>;
  86                 vback-porch = <8>;
  87                 vsync-len = <18>;
  88         };
  89 };
  90
  91 &rk808 {
  92         pinctrl-names = "default";
  93         pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
  94
  95         regulators {
  96                 vcc33_touch: LDO_REG2 {
  97                         regulator-min-microvolt = <3300000>;
  98                         regulator-max-microvolt = <3300000>;
  99                         regulator-name = "vcc33_touch";
 100                         regulator-state-mem {
 101                                 regulator-off-in-suspend;
 102                         };
 103                 };
 104
 105                 vcc5v_touch: SWITCH_REG2 {
 106                         regulator-name = "vcc5v_touch";
 107                         regulator-state-mem {
 108                                 regulator-off-in-suspend;
 109                         };
 110                 };
 111         };
 112 };
 113
 114 &sdmmc {
 115         disable-wp;
 116         pinctrl-names = "default";
 117         pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
 118                         &sdmmc_bus4>;
 119 };
 120
 121 &vcc_5v {
 122         enable-active-high;
 123         gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
 124         pinctrl-names = "default";
 125         pinctrl-0 = <&drv_5v>;
 126 };
 127
 128 &vcc50_hdmi {
 129         enable-active-high;
 130         gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
 131         pinctrl-names = "default";
 132         pinctrl-0 = <&vcc50_hdmi_en>;
 133 };
 134
 135 &gpio0 {
 136         gpio-line-names = "PMIC_SLEEP_AP",
 137                           "DDRIO_PWROFF",
 138                           "DDRIO_RETEN",
 139                           "TS3A227E_INT_L",
 140                           "PMIC_INT_L",
 141                           "PWR_KEY_L",
 142                           "AP_LID_INT_L",
 143                           "EC_IN_RW",
 144
 145                           "AC_PRESENT_AP",
 146                           /*
 147                            * RECOVERY_SW_L is Chrome OS ABI.  Schematics call
 148                            * it REC_MODE_L.
 149                            */
 150                           "RECOVERY_SW_L",
 151                           "OTP_OUT",
 152                           "HOST1_PWR_EN",
 153                           "USBOTG_PWREN_H",
 154                           "AP_WARM_RESET_H",
 155                           "nFALUT2",
 156                           "I2C0_SDA_PMIC",
 157
 158                           "I2C0_SCL_PMIC",
 159                           "SUSPEND_L",
 160                           "USB_INT";
 161 };
 162
 163 &gpio2 {
 164         gpio-line-names = "CONFIG0",
 165                           "CONFIG1",
 166                           "CONFIG2",
 167                           "",
 168                           "",
 169                           "",
 170                           "",
 171                           "CONFIG3",
 172
 173                           "PROCHOT#",
 174                           "EMMC_RST_L",
 175                           "",
 176                           "",
 177                           "BL_PWR_EN",
 178                           "AVDD_1V8_DISP_EN",
 179                           "TOUCH_INT",
 180                           "TOUCH_RST",
 181
 182                           "I2C3_SCL_TP",
 183                           "I2C3_SDA_TP";
 184 };
 185
 186 &gpio3 {
 187         gpio-line-names = "FLASH0_D0",
 188                           "FLASH0_D1",
 189                           "FLASH0_D2",
 190                           "FLASH0_D3",
 191                           "FLASH0_D4",
 192                           "FLASH0_D5",
 193                           "FLASH0_D6",
 194                           "FLASH0_D7",
 195
 196                           "",
 197                           "",
 198                           "",
 199                           "",
 200                           "",
 201                           "",
 202                           "",
 203                           "",
 204
 205                           "FLASH0_CS2/EMMC_CMD",
 206                           "",
 207                           "FLASH0_DQS/EMMC_CLKO";
 208 };
 209
 210 &gpio4 {
 211         gpio-line-names = "",
 212                           "",
 213                           "",
 214                           "",
 215                           "",
 216                           "",
 217                           "",
 218                           "",
 219
 220                           "",
 221                           "",
 222                           "",
 223                           "",
 224                           "",
 225                           "",
 226                           "",
 227                           "",
 228
 229                           "UART0_RXD",
 230                           "UART0_TXD",
 231                           "UART0_CTS",
 232                           "UART0_RTS",
 233                           "SDIO0_D0",
 234                           "SDIO0_D1",
 235                           "SDIO0_D2",
 236                           "SDIO0_D3",
 237
 238                           "SDIO0_CMD",
 239                           "SDIO0_CLK",
 240                           "dev_wake",
 241                           "",
 242                           "WIFI_ENABLE_H",
 243                           "BT_ENABLE_L",
 244                           "WIFI_HOST_WAKE",
 245                           "BT_HOST_WAKE";
 246 };
 247
 248 &gpio5 {
 249         gpio-line-names = "",
 250                           "",
 251                           "",
 252                           "",
 253                           "",
 254                           "",
 255                           "",
 256                           "",
 257
 258                           "",
 259                           "",
 260                           "Volum_Up#",
 261                           "Volum_Down#",
 262                           "SPI0_CLK",
 263                           "SPI0_CS0",
 264                           "SPI0_TXD",
 265                           "SPI0_RXD",
 266
 267                           "",
 268                           "",
 269                           "",
 270                           "VCC50_HDMI_EN";
 271 };
 272
 273 &gpio6 {
 274         gpio-line-names = "I2S0_SCLK",
 275                           "I2S0_LRCK_RX",
 276                           "I2S0_LRCK_TX",
 277                           "I2S0_SDI",
 278                           "I2S0_SDO0",
 279                           "HP_DET_H",
 280                           "",
 281                           "INT_CODEC",
 282
 283                           "I2S0_CLK",
 284                           "I2C2_SDA",
 285                           "I2C2_SCL",
 286                           "MICDET",
 287                           "",
 288                           "",
 289                           "",
 290                           "",
 291
 292                           "SDMMC_D0",
 293                           "SDMMC_D1",
 294                           "SDMMC_D2",
 295                           "SDMMC_D3",
 296                           "SDMMC_CLK",
 297                           "SDMMC_CMD";
 298 };
 299
 300 &gpio7 {
 301         gpio-line-names = "LCDC_BL",
 302                           "PWM_LOG",
 303                           "BL_EN",
 304                           "TRACKPAD_INT",
 305                           "TPM_INT_H",
 306                           "SDMMC_DET_L",
 307                           /*
 308                            * AP_FLASH_WP_L is Chrome OS ABI.  Schematics call
 309                            * it FW_WP_AP.
 310                            */
 311                           "AP_FLASH_WP_L",
 312                           "EC_INT",
 313
 314                           "CPU_NMI",
 315                           "DVS_OK",
 316                           "SDMMC_WP",
 317                           "EDP_HPD",
 318                           "DVS1",
 319                           "nFALUT1",
 320                           "LCD_EN",
 321                           "DVS2",
 322
 323                           "VCC5V_GOOD_H",
 324                           "I2C4_SDA_TP",
 325                           "I2C4_SCL_TP",
 326                           "I2C5_SDA_HDMI",
 327                           "I2C5_SCL_HDMI",
 328                           "5V_DRV",
 329                           "UART2_RXD",
 330                           "UART2_TXD";
 331 };
 332
 333 &gpio8 {
 334         gpio-line-names = "RAM_ID0",
 335                           "RAM_ID1",
 336                           "RAM_ID2",
 337                           "RAM_ID3",
 338                           "I2C1_SDA_TPM",
 339                           "I2C1_SCL_TPM",
 340                           "SPI2_CLK",
 341                           "SPI2_CS0",
 342
 343                           "SPI2_RXD",
 344                           "SPI2_TXD";
 345 };
 346
 347 &pinctrl {
 348         pinctrl-names = "default", "sleep";
 349         pinctrl-0 = <
 350                 /* Common for sleep and wake, but no owners */
 351                 &ddr0_retention
 352                 &ddrio_pwroff
 353                 &global_pwroff
 354
 355                 /* Wake only */
 356                 &suspend_l_wake
 357         >;
 358         pinctrl-1 = <
 359                 /* Common for sleep and wake, but no owners */
 360                 &ddr0_retention
 361                 &ddrio_pwroff
 362                 &global_pwroff
 363
 364                 /* Sleep only */
 365                 &suspend_l_sleep
 366         >;
 367
 368         buck-5v {
 369                 drv_5v: drv-5v {
 370                         rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
 371                 };
 372         };
 373
 374         buttons {
 375                 volum_down_l: volum-down-l {
 376                         rockchip,pins = <5 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;
 377                 };
 378
 379                 volum_up_l: volum-up-l {
 380                         rockchip,pins = <5 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
 381                 };
 382         };
 383
 384         hdmi {
 385                 vcc50_hdmi_en: vcc50-hdmi-en {
 386                         rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
 387                 };
 388         };
 389
 390         pmic {
 391                 dvs_1: dvs-1 {
 392                         rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
 393                 };
 394
 395                 dvs_2: dvs-2 {
 396                         rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
 397                 };
 398         };
 399
 400         prochot {
 401                 gpio_prochot: gpio-prochot {
 402                         rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
 403                 };
 404         };
 405
 406         touchscreen {
 407                 touch_int: touch-int {
 408                         rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
 409                 };
 410
 411                 touch_rst: touch-rst {
 412                         rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
 413                 };
 414         };
 415 };