arch/arm/boot/dts/vf610-cosmic.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  * Copyright 2013 Linaro Limited
   5  */
   6
   7 /dts-v1/;
   8 #include "vf610.dtsi"
   9
  10 / {
  11         model = "PHYTEC Cosmic/Cosmic+ Board";
  12         compatible = "phytec,vf610-cosmic", "fsl,vf610";
  13
  14         chosen {
  15                 bootargs = "console=ttyLP1,115200";
  16         };
  17
  18         memory@80000000 {
  19                 device_type = "memory";
  20                 reg = <0x80000000 0x10000000>;
  21         };
  22
  23         enet_ext: enet_ext {
  24                 compatible = "fixed-clock";
  25                 #clock-cells = <0>;
  26                 clock-frequency = <50000000>;
  27         };
  28 };
  29
  30 &clks {
  31         clocks = <&sxosc>, <&fxosc>, <&enet_ext>;
  32         clock-names = "sxosc", "fxosc", "enet_ext";
  33 };
  34
  35 &esdhc1 {
  36         pinctrl-names = "default";
  37         pinctrl-0 = <&pinctrl_esdhc1>;
  38         bus-width = <4>;
  39         status = "okay";
  40 };
  41
  42 &fec1 {
  43         phy-mode = "rmii";
  44         pinctrl-names = "default";
  45         pinctrl-0 = <&pinctrl_fec1>;
  46         status = "okay";
  47 };
  48
  49 &iomuxc {
  50         vf610-cosmic {
  51                 pinctrl_esdhc1: esdhc1grp {
  52                         fsl,pins = <
  53                                 VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
  54                                 VF610_PAD_PTA25__ESDHC1_CMD     0x31ef
  55                                 VF610_PAD_PTA26__ESDHC1_DAT0    0x31ef
  56                                 VF610_PAD_PTA27__ESDHC1_DAT1    0x31ef
  57                                 VF610_PAD_PTA28__ESDHC1_DATA2   0x31ef
  58                                 VF610_PAD_PTA29__ESDHC1_DAT3    0x31ef
  59                                 VF610_PAD_PTB28__GPIO_98        0x219d
  60                         >;
  61                 };
  62
  63                 pinctrl_fec1: fec1grp {
  64                         fsl,pins = <
  65                                 VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
  66                                 VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
  67                                 VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
  68                                 VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30d1
  69                                 VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
  70                                 VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
  71                                 VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
  72                                 VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
  73                                 VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
  74                         >;
  75                 };
  76
  77                 pinctrl_uart1: uart1grp {
  78                         fsl,pins = <
  79                                 VF610_PAD_PTB4__UART1_TX                0x21a2
  80                                 VF610_PAD_PTB5__UART1_RX                0x21a1
  81                         >;
  82                 };
  83         };
  84 };
  85
  86 &uart1 {
  87         pinctrl-names = "default";
  88         pinctrl-0 = <&pinctrl_uart1>;
  89         status = "okay";
  90 };