arch/arm/mach-imx/iim.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /*
   3  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   4  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   5  */
   6
   7 #ifndef __ASM_ARCH_MXC_IIM_H__
   8 #define __ASM_ARCH_MXC_IIM_H__
   9
  10 /* Register offsets */
  11 #define MXC_IIMSTAT             0x0000
  12 #define MXC_IIMSTATM            0x0004
  13 #define MXC_IIMERR              0x0008
  14 #define MXC_IIMEMASK            0x000C
  15 #define MXC_IIMFCTL             0x0010
  16 #define MXC_IIMUA               0x0014
  17 #define MXC_IIMLA               0x0018
  18 #define MXC_IIMSDAT             0x001C
  19 #define MXC_IIMPREV             0x0020
  20 #define MXC_IIMSREV             0x0024
  21 #define MXC_IIMPRG_P            0x0028
  22 #define MXC_IIMSCS0             0x002C
  23 #define MXC_IIMSCS1             0x0030
  24 #define MXC_IIMSCS2             0x0034
  25 #define MXC_IIMSCS3             0x0038
  26 #define MXC_IIMFBAC0            0x0800
  27 #define MXC_IIMJAC              0x0804
  28 #define MXC_IIMHWV1             0x0808
  29 #define MXC_IIMHWV2             0x080C
  30 #define MXC_IIMHAB0             0x0810
  31 #define MXC_IIMHAB1             0x0814
  32 /* Definitions for i.MX27 TO2 */
  33 #define MXC_IIMMAC              0x0814
  34 #define MXC_IIMPREV_FUSE        0x0818
  35 #define MXC_IIMSREV_FUSE        0x081C
  36 #define MXC_IIMSJC_CHALL_0      0x0820
  37 #define MXC_IIMSJC_CHALL_7      0x083C
  38 #define MXC_IIMFB0UC17          0x0840
  39 #define MXC_IIMFB0UC255         0x0BFC
  40 #define MXC_IIMFBAC1            0x0C00
  41 /* Definitions for i.MX27 TO2 */
  42 #define MXC_IIMSUID             0x0C04
  43 #define MXC_IIMKEY0             0x0C04
  44 #define MXC_IIMKEY20            0x0C54
  45 #define MXC_IIMSJC_RESP_0       0x0C58
  46 #define MXC_IIMSJC_RESP_7       0x0C74
  47 #define MXC_IIMFB1UC30          0x0C78
  48 #define MXC_IIMFB1UC255         0x0FFC
  49
  50 /* Bit definitions */
  51
  52 #define MXC_IIMHWV1_WLOCK               (0x1 << 7)
  53 #define MXC_IIMHWV1_MCU_ENDIAN          (0x1 << 6)
  54 #define MXC_IIMHWV1_DSP_ENDIAN          (0x1 << 5)
  55 #define MXC_IIMHWV1_BOOT_INT            (0x1 << 4)
  56 #define MXC_IIMHWV1_SCC_DISABLE         (0x1 << 3)
  57 #define MXC_IIMHWV1_HANTRO_DISABLE      (0x1 << 2)
  58 #define MXC_IIMHWV1_MEMSTICK_DIS        (0x1 << 1)
  59
  60 #define MXC_IIMHWV2_WLOCK               (0x1 << 7)
  61 #define MXC_IIMHWV2_BP_SDMA             (0x1 << 6)
  62 #define MXC_IIMHWV2_SCM_DCM             (0x1 << 5)
  63
  64 #endif /* __ASM_ARCH_MXC_IIM_H__ */