1 // SPDX-License-Identifier: GPL-2.0
5 compatible = "brcm,bcm7358";
11 mips-hpt-frequency = <375000000>;
14 compatible = "brcm,bmips3300";
24 cpu_intc: interrupt-controller {
26 compatible = "mti,cpu-interrupt-controller";
29 #interrupt-cells = <1>;
34 compatible = "fixed-clock";
36 clock-frequency = <81000000>;
40 compatible = "fixed-clock";
42 clock-frequency = <27000000>;
50 compatible = "simple-bus";
51 ranges = <0 0x10000000 0x01000000>;
53 periph_intc: interrupt-controller@411400 {
54 compatible = "brcm,bcm7038-l1-intc";
55 reg = <0x411400 0x30>;
58 #interrupt-cells = <1>;
60 interrupt-parent = <&cpu_intc>;
64 sun_l2_intc: interrupt-controller@403000 {
65 compatible = "brcm,l2-intc";
66 reg = <0x403000 0x30>;
68 #interrupt-cells = <1>;
69 interrupt-parent = <&periph_intc>;
74 compatible = "brcm,bcm7400-gisb-arb";
75 reg = <0x400000 0xdc>;
77 interrupt-parent = <&sun_l2_intc>;
78 interrupts = <0>, <2>;
79 brcm,gisb-arb-master-mask = <0x2f3>;
80 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
85 upg_irq0_intc: interrupt-controller@406600 {
86 compatible = "brcm,bcm7120-l2-intc";
89 brcm,int-map-mask = <0x44>, <0x7000000>;
90 brcm,int-fwd-mask = <0x70000>;
93 #interrupt-cells = <1>;
95 interrupt-parent = <&periph_intc>;
96 interrupts = <56>, <54>;
97 interrupt-names = "upg_main", "upg_bsc";
100 upg_aon_irq0_intc: interrupt-controller@408b80 {
101 compatible = "brcm,bcm7120-l2-intc";
102 reg = <0x408b80 0x8>;
104 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
105 brcm,int-fwd-mask = <0>;
108 interrupt-controller;
109 #interrupt-cells = <1>;
111 interrupt-parent = <&periph_intc>;
112 interrupts = <57>, <55>, <59>;
113 interrupt-names = "upg_main_aon", "upg_bsc_aon",
117 sun_top_ctrl: syscon@404000 {
118 compatible = "brcm,bcm7358-sun-top-ctrl", "syscon";
119 reg = <0x404000 0x51c>;
124 compatible = "brcm,brcmstb-reboot";
125 syscon = <&sun_top_ctrl 0x304 0x308>;
128 uart0: serial@406800 {
129 compatible = "ns16550a";
130 reg = <0x406800 0x20>;
131 reg-io-width = <0x4>;
134 interrupt-parent = <&periph_intc>;
136 clocks = <&uart_clk>;
140 uart1: serial@406840 {
141 compatible = "ns16550a";
142 reg = <0x406840 0x20>;
143 reg-io-width = <0x4>;
146 interrupt-parent = <&periph_intc>;
148 clocks = <&uart_clk>;
152 uart2: serial@406880 {
153 compatible = "ns16550a";
154 reg = <0x406880 0x20>;
155 reg-io-width = <0x4>;
158 interrupt-parent = <&periph_intc>;
160 clocks = <&uart_clk>;
165 clock-frequency = <390000>;
166 compatible = "brcm,brcmstb-i2c";
167 interrupt-parent = <&upg_irq0_intc>;
168 reg = <0x406200 0x58>;
170 interrupt-names = "upg_bsca";
175 clock-frequency = <390000>;
176 compatible = "brcm,brcmstb-i2c";
177 interrupt-parent = <&upg_irq0_intc>;
178 reg = <0x406280 0x58>;
180 interrupt-names = "upg_bscb";
185 clock-frequency = <390000>;
186 compatible = "brcm,brcmstb-i2c";
187 interrupt-parent = <&upg_irq0_intc>;
188 reg = <0x406300 0x58>;
190 interrupt-names = "upg_bscc";
195 clock-frequency = <390000>;
196 compatible = "brcm,brcmstb-i2c";
197 interrupt-parent = <&upg_aon_irq0_intc>;
198 reg = <0x408980 0x58>;
200 interrupt-names = "upg_bscd";
205 compatible = "brcm,bcm7038-pwm";
206 reg = <0x406400 0x28>;
213 compatible = "brcm,bcm7038-pwm";
214 reg = <0x406700 0x28>;
220 watchdog: watchdog@4066a8 {
222 compatible = "brcm,bcm7038-wdt";
223 reg = <0x4066a8 0x14>;
227 aon_pm_l2_intc: interrupt-controller@408240 {
228 compatible = "brcm,l2-intc";
229 reg = <0x408240 0x30>;
230 interrupt-controller;
231 #interrupt-cells = <1>;
232 interrupt-parent = <&periph_intc>;
237 upg_gio: gpio@406500 {
238 compatible = "brcm,brcmstb-gpio";
239 reg = <0x406500 0xa0>;
241 #interrupt-cells = <2>;
243 interrupt-controller;
244 interrupt-parent = <&upg_irq0_intc>;
246 brcm,gpio-bank-widths = <32 32 32 29 4>;
249 upg_gio_aon: gpio@408c00 {
250 compatible = "brcm,brcmstb-gpio";
251 reg = <0x408c00 0x60>;
253 #interrupt-cells = <2>;
255 interrupt-controller;
256 interrupt-parent = <&upg_aon_irq0_intc>;
258 interrupts-extended = <&upg_aon_irq0_intc 6>,
261 brcm,gpio-bank-widths = <21 32 2>;
264 enet0: ethernet@430000 {
265 phy-mode = "internal";
266 phy-handle = <&phy1>;
267 mac-address = [ 00 10 18 36 23 1a ];
268 compatible = "brcm,genet-v2";
269 #address-cells = <0x1>;
271 reg = <0x430000 0x4c8c>;
272 interrupts = <24>, <25>;
273 interrupt-parent = <&periph_intc>;
277 compatible = "brcm,genet-mdio-v2";
278 #address-cells = <0x1>;
282 phy1: ethernet-phy@1 {
285 compatible = "brcm,40nm-ephy",
286 "ethernet-phy-ieee802.3-c22";
292 compatible = "brcm,bcm7358-ehci", "generic-ehci";
293 reg = <0x480300 0x100>;
295 interrupt-parent = <&periph_intc>;
301 compatible = "brcm,bcm7358-ohci", "generic-ohci";
302 reg = <0x480400 0x100>;
305 interrupt-parent = <&periph_intc>;
310 hif_l2_intc: interrupt-controller@411000 {
311 compatible = "brcm,l2-intc";
312 reg = <0x411000 0x30>;
313 interrupt-controller;
314 #interrupt-cells = <1>;
315 interrupt-parent = <&periph_intc>;
320 compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
321 #address-cells = <1>;
324 reg = <0x412800 0x400>;
325 interrupt-parent = <&hif_l2_intc>;
330 spi_l2_intc: interrupt-controller@411d00 {
331 compatible = "brcm,l2-intc";
332 reg = <0x411d00 0x30>;
333 interrupt-controller;
334 #interrupt-cells = <1>;
335 interrupt-parent = <&periph_intc>;
340 #address-cells = <0x1>;
342 compatible = "brcm,spi-bcm-qspi",
343 "brcm,spi-brcmstb-qspi";
345 reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
346 reg-names = "cs_reg", "hif_mspi", "bspi";
347 interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
348 interrupt-parent = <&spi_l2_intc>;
349 interrupt-names = "spi_lr_fullness_reached",
350 "spi_lr_session_aborted",
352 "spi_lr_session_done",
360 #address-cells = <1>;
362 compatible = "brcm,spi-bcm-qspi",
363 "brcm,spi-brcmstb-mspi";
365 reg = <0x408a00 0x180>;
368 interrupt-parent = <&upg_aon_irq0_intc>;
369 interrupt-names = "mspi_done";
373 waketimer: waketimer@408e80 {
374 compatible = "brcm,brcmstb-waketimer";
375 reg = <0x408e80 0x14>;
377 interrupt-parent = <&aon_pm_l2_intc>;
378 interrupt-names = "timer";