1 // SPDX-License-Identifier: GPL-2.0
5 compatible = "brcm,bcm7360";
11 mips-hpt-frequency = <375000000>;
14 compatible = "brcm,bmips3300";
24 cpu_intc: interrupt-controller {
26 compatible = "mti,cpu-interrupt-controller";
29 #interrupt-cells = <1>;
34 compatible = "fixed-clock";
36 clock-frequency = <81000000>;
40 compatible = "fixed-clock";
42 clock-frequency = <27000000>;
50 compatible = "simple-bus";
51 ranges = <0 0x10000000 0x01000000>;
53 periph_intc: interrupt-controller@411400 {
54 compatible = "brcm,bcm7038-l1-intc";
55 reg = <0x411400 0x30>;
58 #interrupt-cells = <1>;
60 interrupt-parent = <&cpu_intc>;
64 sun_l2_intc: interrupt-controller@403000 {
65 compatible = "brcm,l2-intc";
66 reg = <0x403000 0x30>;
68 #interrupt-cells = <1>;
69 interrupt-parent = <&periph_intc>;
74 compatible = "brcm,bcm7400-gisb-arb";
75 reg = <0x400000 0xdc>;
77 interrupt-parent = <&sun_l2_intc>;
78 interrupts = <0>, <2>;
79 brcm,gisb-arb-master-mask = <0x2f3>;
80 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
85 upg_irq0_intc: interrupt-controller@406600 {
86 compatible = "brcm,bcm7120-l2-intc";
89 brcm,int-map-mask = <0x44>, <0x7000000>;
90 brcm,int-fwd-mask = <0x70000>;
93 #interrupt-cells = <1>;
95 interrupt-parent = <&periph_intc>;
96 interrupts = <56>, <54>;
97 interrupt-names = "upg_main", "upg_bsc";
100 upg_aon_irq0_intc: interrupt-controller@408b80 {
101 compatible = "brcm,bcm7120-l2-intc";
102 reg = <0x408b80 0x8>;
104 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
105 brcm,int-fwd-mask = <0>;
108 interrupt-controller;
109 #interrupt-cells = <1>;
111 interrupt-parent = <&periph_intc>;
112 interrupts = <57>, <55>, <59>;
113 interrupt-names = "upg_main_aon", "upg_bsc_aon",
117 sun_top_ctrl: syscon@404000 {
118 compatible = "brcm,bcm7360-sun-top-ctrl", "syscon";
119 reg = <0x404000 0x51c>;
124 compatible = "brcm,brcmstb-reboot";
125 syscon = <&sun_top_ctrl 0x304 0x308>;
128 uart0: serial@406800 {
129 compatible = "ns16550a";
130 reg = <0x406800 0x20>;
131 reg-io-width = <0x4>;
134 interrupt-parent = <&periph_intc>;
136 clocks = <&uart_clk>;
140 uart1: serial@406840 {
141 compatible = "ns16550a";
142 reg = <0x406840 0x20>;
143 reg-io-width = <0x4>;
146 interrupt-parent = <&periph_intc>;
148 clocks = <&uart_clk>;
152 uart2: serial@406880 {
153 compatible = "ns16550a";
154 reg = <0x406880 0x20>;
155 reg-io-width = <0x4>;
158 interrupt-parent = <&periph_intc>;
160 clocks = <&uart_clk>;
165 clock-frequency = <390000>;
166 compatible = "brcm,brcmstb-i2c";
167 interrupt-parent = <&upg_irq0_intc>;
168 reg = <0x406200 0x58>;
170 interrupt-names = "upg_bsca";
175 clock-frequency = <390000>;
176 compatible = "brcm,brcmstb-i2c";
177 interrupt-parent = <&upg_irq0_intc>;
178 reg = <0x406280 0x58>;
180 interrupt-names = "upg_bscb";
185 clock-frequency = <390000>;
186 compatible = "brcm,brcmstb-i2c";
187 interrupt-parent = <&upg_irq0_intc>;
188 reg = <0x406300 0x58>;
190 interrupt-names = "upg_bscc";
195 clock-frequency = <390000>;
196 compatible = "brcm,brcmstb-i2c";
197 interrupt-parent = <&upg_aon_irq0_intc>;
198 reg = <0x408980 0x58>;
200 interrupt-names = "upg_bscd";
205 compatible = "brcm,bcm7038-pwm";
206 reg = <0x406400 0x28>;
212 watchdog: watchdog@4066a8 {
214 compatible = "brcm,bcm7038-wdt";
215 reg = <0x4066a8 0x14>;
219 aon_pm_l2_intc: interrupt-controller@408440 {
220 compatible = "brcm,l2-intc";
221 reg = <0x408440 0x30>;
222 interrupt-controller;
223 #interrupt-cells = <1>;
224 interrupt-parent = <&periph_intc>;
229 aon_ctrl: syscon@408000 {
230 compatible = "brcm,brcmstb-aon-ctrl";
231 reg = <0x408000 0x100>, <0x408200 0x200>;
232 reg-names = "aon-ctrl", "aon-sram";
235 timers: timer@406680 {
236 compatible = "brcm,brcmstb-timers";
237 reg = <0x406680 0x40>;
240 upg_gio: gpio@406500 {
241 compatible = "brcm,brcmstb-gpio";
242 reg = <0x406500 0xa0>;
244 #interrupt-cells = <2>;
246 interrupt-controller;
247 interrupt-parent = <&upg_irq0_intc>;
249 brcm,gpio-bank-widths = <32 32 32 29 4>;
252 upg_gio_aon: gpio@408c00 {
253 compatible = "brcm,brcmstb-gpio";
254 reg = <0x408c00 0x60>;
256 #interrupt-cells = <2>;
258 interrupt-controller;
259 interrupt-parent = <&upg_aon_irq0_intc>;
261 interrupts-extended = <&upg_aon_irq0_intc 6>,
264 brcm,gpio-bank-widths = <21 32 2>;
267 enet0: ethernet@430000 {
268 phy-mode = "internal";
269 phy-handle = <&phy1>;
270 mac-address = [ 00 10 18 36 23 1a ];
271 compatible = "brcm,genet-v2";
272 #address-cells = <0x1>;
274 reg = <0x430000 0x4c8c>;
275 interrupts = <24>, <25>;
276 interrupt-parent = <&periph_intc>;
280 compatible = "brcm,genet-mdio-v2";
281 #address-cells = <0x1>;
285 phy1: ethernet-phy@1 {
288 compatible = "brcm,40nm-ephy",
289 "ethernet-phy-ieee802.3-c22";
295 compatible = "brcm,bcm7360-ehci", "generic-ehci";
296 reg = <0x480300 0x100>;
298 interrupt-parent = <&periph_intc>;
304 compatible = "brcm,bcm7360-ohci", "generic-ohci";
305 reg = <0x480400 0x100>;
308 interrupt-parent = <&periph_intc>;
313 hif_l2_intc: interrupt-controller@411000 {
314 compatible = "brcm,l2-intc";
315 reg = <0x411000 0x30>;
316 interrupt-controller;
317 #interrupt-cells = <1>;
318 interrupt-parent = <&periph_intc>;
323 compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
324 #address-cells = <1>;
327 reg = <0x412800 0x400>;
328 interrupt-parent = <&hif_l2_intc>;
334 compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
335 reg-names = "ahci", "top-ctrl";
336 reg = <0x181000 0xa9c>, <0x180020 0x1c>;
337 interrupt-parent = <&periph_intc>;
339 #address-cells = <1>;
354 sata_phy: sata-phy@180100 {
355 compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
356 reg = <0x180100 0x0eff>;
358 #address-cells = <1>;
362 sata_phy0: sata-phy@0 {
367 sata_phy1: sata-phy@1 {
373 sdhci0: sdhci@410000 {
374 compatible = "brcm,bcm7425-sdhci";
375 reg = <0x410000 0x100>;
376 interrupt-parent = <&periph_intc>;
381 spi_l2_intc: interrupt-controller@411d00 {
382 compatible = "brcm,l2-intc";
383 reg = <0x411d00 0x30>;
384 interrupt-controller;
385 #interrupt-cells = <1>;
386 interrupt-parent = <&periph_intc>;
391 #address-cells = <0x1>;
393 compatible = "brcm,spi-bcm-qspi",
394 "brcm,spi-brcmstb-qspi";
396 reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
397 reg-names = "cs_reg", "hif_mspi", "bspi";
398 interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
399 interrupt-parent = <&spi_l2_intc>;
400 interrupt-names = "spi_lr_fullness_reached",
401 "spi_lr_session_aborted",
403 "spi_lr_session_done",
411 #address-cells = <1>;
413 compatible = "brcm,spi-bcm-qspi",
414 "brcm,spi-brcmstb-mspi";
416 reg = <0x408a00 0x180>;
419 interrupt-parent = <&upg_aon_irq0_intc>;
420 interrupt-names = "mspi_done";
424 waketimer: waketimer@408e80 {
425 compatible = "brcm,brcmstb-waketimer";
426 reg = <0x408e80 0x14>;
428 interrupt-parent = <&aon_pm_l2_intc>;
429 interrupt-names = "timer";
436 compatible = "simple-bus";
437 ranges = <0x0 0x103b0000 0xa000>;
438 #address-cells = <1>;
441 memory-controller@0 {
442 compatible = "brcm,brcmstb-memc", "simple-bus";
443 ranges = <0x0 0x0 0xa000>;
444 #address-cells = <1>;
448 compatible = "brcm,brcmstb-memc-arb";
449 reg = <0x1000 0x248>;
453 compatible = "brcm,brcmstb-memc-ddr";
454 reg = <0x2000 0x300>;
458 compatible = "brcm,brcmstb-ddr-phy";
463 compatible = "brcm,brcmstb-ddr-shimphy";
464 reg = <0x8000 0x13c>;