arch/mips/boot/dts/mscc/jaguar2_pcb111.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2018 Microsemi Corporation
   4  */
   5
   6 /dts-v1/;
   7 #include "jaguar2_common.dtsi"
   8
   9 / {
  10         model = "Jaguar2 Cu48 PCB111 Reference Board";
  11         compatible = "mscc,jr2-pcb111", "mscc,jr2";
  12
  13         aliases {
  14                 i2c0    = &i2c0;
  15                 i2c149  = &i2c149;
  16                 i2c150  = &i2c150;
  17                 i2c151  = &i2c151;
  18                 i2c152  = &i2c152;
  19                 i2c203  = &i2c203;
  20         };
  21
  22         i2c0_imux: i2c0-imux {
  23                 compatible = "i2c-mux-pinctrl";
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26                 i2c-parent = <&i2c0>;
  27                 pinctrl-names =
  28                         "i2c149", "i2c150", "i2c151", "i2c152", "i2c203", "idle";
  29                 pinctrl-0 = <&i2cmux_0>;
  30                 pinctrl-1 = <&i2cmux_1>;
  31                 pinctrl-2 = <&i2cmux_2>;
  32                 pinctrl-3 = <&i2cmux_3>;
  33                 pinctrl-4 = <&i2cmux_pins_i>; // Added by convention for PoE
  34                 pinctrl-5 = <&i2cmux_pins_i>;
  35                 i2c149: i2c@0 {
  36                         reg = <0x0>;
  37                         #address-cells = <1>;
  38                         #size-cells = <0>;
  39                 };
  40                 i2c150: i2c@1 {
  41                         reg = <0x1>;
  42                         #address-cells = <1>;
  43                         #size-cells = <0>;
  44                 };
  45                 i2c151: i2c@2 {
  46                         reg = <0x2>;
  47                         #address-cells = <1>;
  48                         #size-cells = <0>;
  49                 };
  50                 i2c152: i2c@3 {
  51                         reg = <0x3>;
  52                         #address-cells = <1>;
  53                         #size-cells = <0>;
  54                 };
  55                 i2c203: i2c@4 {
  56                         reg = <0x4>;
  57                         #address-cells = <1>;
  58                         #size-cells = <0>;
  59                 };
  60         };
  61 };
  62
  63 &gpio {
  64         synce_builtin_pins: synce-builtin-pins {
  65                 // GPIO 49 == SI_nCS13
  66                 pins = "GPIO_49";
  67                 function = "si";
  68         };
  69         cpld_pins: cpld-pins {
  70                 // GPIO 50 == SI_nCS14
  71                 pins = "GPIO_50";
  72                 function = "si";
  73         };
  74         cpld_fifo_pins: synce-builtin-pins {
  75                 // GPIO 51 == SI_nCS15
  76                 pins = "GPIO_51";
  77                 function = "si";
  78         };
  79 };
  80
  81 &gpio {
  82         i2cmux_pins_i: i2cmux-pins-i {
  83                 pins = "GPIO_17", "GPIO_18";
  84                 function = "twi_scl_m";
  85                 output-low;
  86         };
  87         i2cmux_0: i2cmux-0 {
  88                 pins = "GPIO_17";
  89                 function = "twi_scl_m";
  90                 output-high;
  91         };
  92         i2cmux_1: i2cmux-1 {
  93                 pins = "GPIO_18";
  94                 function = "twi_scl_m";
  95                 output-high;
  96         };
  97         i2cmux_2: i2cmux-2 {
  98                 pins = "GPIO_20";
  99                 function = "twi_scl_m";
 100                 output-high;
 101         };
 102         i2cmux_3: i2cmux-3 {
 103                 pins = "GPIO_21";
 104                 function = "twi_scl_m";
 105                 output-high;
 106         };
 107 };