arch/mips/cavium-octeon/executive/cvmx-helper-errata.c

   1 /***********************license start***************
   2  * Author: Cavium Networks
   3  *
   4  * Contact: support@caviumnetworks.com
   5  * This file is part of the OCTEON SDK
   6  *
   7  * Copyright (c) 2003-2008 Cavium Networks
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this file; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22  * or visit http://www.gnu.org/licenses/.
  23  *
  24  * This file may also be available under a different license from Cavium.
  25  * Contact Cavium Networks for more information
  26  ***********************license end**************************************/
  27
  28 /**
  29  *
  30  * Fixes and workaround for Octeon chip errata. This file
  31  * contains functions called by cvmx-helper to workaround known
  32  * chip errata. For the most part, code doesn't need to call
  33  * these functions directly.
  34  *
  35  */
  36 #include <linux/export.h>
  37
  38 #include <asm/octeon/octeon.h>
  39
  40 #include <asm/octeon/cvmx-helper-jtag.h>
  41
  42 /**
  43  * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
  44  * 1 doesn't work properly. The following code disables 2nd order
  45  * CDR for the specified QLM.
  46  *
  47  * @qlm:    QLM to disable 2nd order CDR for.
  48  */
  49 void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm)
  50 {
  51         int lane;
  52         cvmx_helper_qlm_jtag_init();
  53         /* We need to load all four lanes of the QLM, a total of 1072 bits */
  54         for (lane = 0; lane < 4; lane++) {
  55                 /*
  56                  * Each lane has 268 bits. We need to set
  57                  * cfg_cdr_incx<67:64> = 3 and cfg_cdr_secord<77> =
  58                  * 1. All other bits are zero. Bits go in LSB first,
  59                  * so start off with the zeros for bits <63:0>.
  60                  */
  61                 cvmx_helper_qlm_jtag_shift_zeros(qlm, 63 - 0 + 1);
  62                 /* cfg_cdr_incx<67:64>=3 */
  63                 cvmx_helper_qlm_jtag_shift(qlm, 67 - 64 + 1, 3);
  64                 /* Zeros for bits <76:68> */
  65                 cvmx_helper_qlm_jtag_shift_zeros(qlm, 76 - 68 + 1);
  66                 /* cfg_cdr_secord<77>=1 */
  67                 cvmx_helper_qlm_jtag_shift(qlm, 77 - 77 + 1, 1);
  68                 /* Zeros for bits <267:78> */
  69                 cvmx_helper_qlm_jtag_shift_zeros(qlm, 267 - 78 + 1);
  70         }
  71         cvmx_helper_qlm_jtag_update(qlm);
  72 }
  73 EXPORT_SYMBOL(__cvmx_helper_errata_qlm_disable_2nd_order_cdr);